Searched refs:PHYCLKPerState (Results 1 – 5 of 5) sorted by relevance
405 double PHYCLKPerState[DC__VOLTAGE_STATES + 1]; member
265 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
4108 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20v2_ModeSupportAndSystemConfigurationFull()4121 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()4150 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()4180 && mode_lib->vba.PHYCLKPerState[i] in dml20v2_ModeSupportAndSystemConfigurationFull()
4064 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20_ModeSupportAndSystemConfigurationFull()4077 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20_ModeSupportAndSystemConfigurationFull()4106 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20_ModeSupportAndSystemConfigurationFull()4136 && mode_lib->vba.PHYCLKPerState[i] in dml20_ModeSupportAndSystemConfigurationFull()
4144 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml21_ModeSupportAndSystemConfigurationFull()4158 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml21_ModeSupportAndSystemConfigurationFull()4189 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml21_ModeSupportAndSystemConfigurationFull()4221 && mode_lib->vba.PHYCLKPerState[i] in dml21_ModeSupportAndSystemConfigurationFull()