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Searched refs:POSTING_READ (Results 1 – 25 of 26) sorted by relevance

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/netbsd/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_hdmi.c321 POSTING_READ(reg); in ibx_write_infoframe()
401 POSTING_READ(reg); in cpt_write_infoframe()
474 POSTING_READ(reg); in vlv_write_infoframe()
894 POSTING_READ(reg); in g4x_set_infoframes()
913 POSTING_READ(reg); in g4x_set_infoframes()
1065 POSTING_READ(reg); in ibx_set_infoframes()
1086 POSTING_READ(reg); in ibx_set_infoframes()
1122 POSTING_READ(reg); in cpt_set_infoframes()
1135 POSTING_READ(reg); in cpt_set_infoframes()
1193 POSTING_READ(reg); in vlv_set_infoframes()
[all …]
H A Dintel_fifo_underrun.c108 POSTING_READ(reg); in i9xx_check_fifo_underruns()
127 POSTING_READ(reg); in i9xx_set_fifo_underrun_reporting()
159 POSTING_READ(GEN7_ERR_INT); in ivb_check_fifo_underruns()
225 POSTING_READ(SERR_INT); in cpt_check_pch_fifo_underruns()
H A Dintel_dpll_mgr.c431 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_enable()
440 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_enable()
450 POSTING_READ(PCH_DPLL(id)); in ibx_pch_dpll_disable()
515 POSTING_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
523 POSTING_READ(SPLL_CTL); in hsw_ddi_spll_enable()
535 POSTING_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
553 POSTING_READ(SPLL_CTL); in hsw_ddi_spll_disable()
1007 POSTING_READ(DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1020 POSTING_READ(regs[id].cfgcr1); in skl_ddi_pll_enable()
1046 POSTING_READ(regs[id].ctl); in skl_ddi_pll_disable()
[all …]
H A Dintel_pipe_crc.c635 POSTING_READ(PIPE_CRC_CTL(crtc->index)); in intel_crtc_set_crc_source()
670 POSTING_READ(PIPE_CRC_CTL(crtc->index)); in intel_crtc_enable_pipe_crc()
685 POSTING_READ(PIPE_CRC_CTL(crtc->index)); in intel_crtc_disable_pipe_crc()
H A Dintel_dsb.c69 POSTING_READ(DSB_CTRL(pipe, dsb->id)); in intel_dsb_enable_engine()
89 POSTING_READ(DSB_CTRL(pipe, dsb->id)); in intel_dsb_disable_engine()
H A Dintel_dp.c2740 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_on()
2805 POSTING_READ(pp_ctrl_reg); in edp_panel_vdd_off_sync()
2899 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
2907 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
2915 POSTING_READ(pp_ctrl_reg); in edp_panel_on()
2960 POSTING_READ(pp_ctrl_reg); in edp_panel_off()
3002 POSTING_READ(pp_ctrl_reg); in _intel_edp_backlight_on()
3130 POSTING_READ(DP_A); in ilk_edp_pll_on()
3145 POSTING_READ(DP_A); in ilk_edp_pll_on()
3164 POSTING_READ(DP_A); in ilk_edp_pll_off()
[all …]
H A Dintel_ddi.c1141 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1171 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1181 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1190 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1212 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1217 POSTING_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1224 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1233 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
2990 POSTING_READ(ICL_DPCLKA_CFGCR0); in icl_map_plls_to_ports()
3996 POSTING_READ(reg); in intel_enable_ddi_hdmi()
[all …]
H A Dintel_panel.c936 POSTING_READ(BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
971 POSTING_READ(BLC_PWM_CPU_CTL2); in pch_enable_backlight()
985 POSTING_READ(BLC_PWM_PCH_CTL1); in pch_enable_backlight()
1014 POSTING_READ(BLC_PWM_CTL); in i9xx_enable_backlight()
1057 POSTING_READ(BLC_PWM_CTL2); in i965_enable_backlight()
1089 POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
1136 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); in bxt_enable_backlight()
1167 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); in cnp_enable_backlight()
H A Dintel_vga.c68 POSTING_READ(vga_reg); in intel_vga_disable()
H A Dintel_display.c1529 POSTING_READ(reg); in i9xx_enable_pll()
1547 POSTING_READ(reg); in i9xx_enable_pll()
1882 POSTING_READ(reg); in intel_enable_pipe()
5009 POSTING_READ(reg); in intel_fdi_normal_train()
5056 POSTING_READ(reg); in ilk_fdi_link_train()
5091 POSTING_READ(reg); in ilk_fdi_link_train()
5137 POSTING_READ(reg); in gen6_fdi_link_train()
5166 POSTING_READ(reg); in gen6_fdi_link_train()
5219 POSTING_READ(reg); in gen6_fdi_link_train()
5270 POSTING_READ(reg); in ivb_manual_fdi_link_train()
[all …]
H A Dintel_lvds.c324 POSTING_READ(lvds_encoder->reg); in intel_enable_lvds()
344 POSTING_READ(lvds_encoder->reg); in intel_disable_lvds()
H A Dintel_crt.c467 POSTING_READ(crt->adpa_reg); in ilk_crt_detect_hotplug()
930 POSTING_READ(crt->adpa_reg); in intel_crt_reset()
H A Dicl_dsi.c340 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
346 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
638 POSTING_READ(ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
H A Dintel_display_power.c4391 POSTING_READ(reg); in intel_dbuf_slice_set()
4447 POSTING_READ(DBUF_CTL_S2); in icl_dbuf_enable()
4466 POSTING_READ(DBUF_CTL_S2); in icl_dbuf_disable()
4569 POSTING_READ(D_COMP_BDW); in hsw_write_dcomp()
4603 POSTING_READ(LCPLL_CTL); in hsw_disable_lcpll()
4621 POSTING_READ(LCPLL_CTL); in hsw_disable_lcpll()
4648 POSTING_READ(LCPLL_CTL); in hsw_restore_lcpll()
H A Dvlv_dsi_pll.c519 POSTING_READ(BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
H A Dintel_cdclk.c974 POSTING_READ(DPLL_CTRL1); in skl_dpll0_enable()
1064 POSTING_READ(CDCLK_CTL); in skl_set_cdclk()
1079 POSTING_READ(CDCLK_CTL); in skl_set_cdclk()
H A Dintel_sdvo.c226 POSTING_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
233 POSTING_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
250 POSTING_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
253 POSTING_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
H A Dintel_tv.c1618 POSTING_READ(TV_DAC); in intel_tv_detect_type()
1647 POSTING_READ(TV_CTL); in intel_tv_detect_type()
H A Dvlv_dsi.c680 POSTING_READ(port_ctrl); in intel_dsi_port_enable()
699 POSTING_READ(port_ctrl); in intel_dsi_port_disable()
H A Dintel_fbc.c216 POSTING_READ(MSG_FBC_REND_STATE); in intel_fbc_recompress()
/netbsd/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_irq.c325 POSTING_READ(DEIMR); in ilk_update_display_irq()
357 POSTING_READ(GEN8_DE_PORT_IMR); in bdw_update_port_irq()
415 POSTING_READ(SDEIMR); in ibx_display_interrupt_update()
479 POSTING_READ(reg); in i915_enable_pipestat()
502 POSTING_READ(reg); in i915_disable_pipestat()
933 POSTING_READ(GEN7_MISCCPCTL); in ivb_parity_work()
952 POSTING_READ(reg); in ivb_parity_work()
2706 POSTING_READ(SDEIER); in ibx_irq_pre_postinstall()
2781 POSTING_READ(VLV_MASTER_IER); in valleyview_irq_reset()
3332 POSTING_READ(VLV_MASTER_IER); in valleyview_irq_postinstall()
[all …]
H A Dintel_csr.c296 POSTING_READ(DC_STATE_DEBUG); in gen9_set_dc_state_debugmask()
H A Dintel_pm.c359 POSTING_READ(FW_BLC_SELF_VLV); in _intel_set_memory_cxsr()
363 POSTING_READ(FW_BLC_SELF); in _intel_set_memory_cxsr()
372 POSTING_READ(DSPFW3); in _intel_set_memory_cxsr()
378 POSTING_READ(FW_BLC_SELF); in _intel_set_memory_cxsr()
389 POSTING_READ(INSTPM); in _intel_set_memory_cxsr()
985 POSTING_READ(DSPFW1); in g4x_write_wm_values()
1064 POSTING_READ(DSPFW1); in vlv_write_wm_values()
6349 POSTING_READ(DSPSURF(pipe)); in g4x_disable_trickle_feed()
6630 POSTING_READ(GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
H A Di915_drv.h2035 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) macro
/netbsd/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Daperture_gm.c153 POSTING_READ(fence_reg_lo); in intel_vgpu_write_fence()
157 POSTING_READ(fence_reg_lo); in intel_vgpu_write_fence()

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