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Searched refs:Q6 (Results 1 – 25 of 36) sorted by relevance

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/netbsd/sys/external/bsd/compiler_rt/dist/lib/xray/
H A Dxray_trampoline_AArch64.S28 STP Q6, Q7, [SP, #-32]!
43 LDP Q6, Q7, [SP], #32
116 STP Q6, Q7, [SP, #-32]!
133 LDP Q6, Q7, [SP], #32
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td105 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
107 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
109 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
111 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
114 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
116 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
149 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
158 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
160 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
240 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
[all …]
H A DAArch64CallingConvention.cpp37 AArch64::Q6, AArch64::Q7};
H A DAArch64PBQPRegAlloc.cpp131 case AArch64::Q6: in isOdd()
H A DAArch64SchedPredicates.td176 CheckRegOperand<0, Q6>,
H A DAArch64RegisterInfo.td397 def Q6 : AArch64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias<B6>;
801 def Z6 : AArch64Reg<6, "z6", [Q6, Z6_HI]>, DwarfRegNum<[102]>;
/netbsd/external/gpl3/gcc/dist/libquadmath/math/
H A Dexpm1q.c75 Q6 = 3.697714952261803935521187272204485251835E3Q, variable
145 + Q6) * x + Q5) * x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1q()
H A Dlog1pq.c82 Q6 = 6.132189329546557743179177159925690841200E5Q, variable
240 + Q6) * x in log1pq()
H A Dacosq.c116 Q6 = 6.745883931909770880159915641984874746358E1Q, variable
223 + Q6) * t in acosq()
/netbsd/external/gpl3/gcc.old/dist/libquadmath/math/
H A Dexpm1q.c75 Q6 = 3.697714952261803935521187272204485251835E3Q, variable
145 + Q6) * x + Q5) * x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1q()
H A Dlog1pq.c82 Q6 = 6.132189329546557743179177159925690841200E5Q, variable
240 + Q6) * x in log1pq()
H A Dacosq.c116 Q6 = 6.745883931909770880159915641984874746358E1Q, variable
223 + Q6) * t in acosq()
/netbsd/lib/libm/src/
H A Db_tgamma.c114 #define Q6 -1.76012741431666995019222898833e-03 macro
255 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8))))))); in ratfun_gam()
/netbsd/lib/libm/noieee_src/
H A Dn_gamma.c104 #define Q6 -1.76012741431666995019222898833e-03 macro
269 q = Q0 +z*(Q1+z*(Q2+z*(Q3+z*(Q4+z*(Q5+z*(Q6+z*(Q7+z*Q8))))))); in ratfun_gam()
/netbsd/tests/usr.bin/xlint/lint1/
H A Dqueries.c158 Q6(int i) in Q6() function
/netbsd/external/gpl3/gcc.old/dist/libgcc/config/avr/libf7/
H A Dlibf7-asm.sx1091 #define Q6 16
1092 #define Q7 Q6+1
1119 wmov Q6, Q0
1169 rol Q6
1177 wmov C5, Q6
/netbsd/external/gpl3/gcc/dist/libgcc/config/avr/libf7/
H A Dlibf7-asm.sx1091 #define Q6 16
1092 #define Q7 Q6+1
1119 wmov Q6, Q0
1169 rol Q6
1177 wmov C5, Q6
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp312 {codeview::RegisterId::ARM_NQ6, ARM::Q6}, in initLLVMToCVRegMapping()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp205 {codeview::RegisterId::ARM64_Q6, AArch64::Q6}, in initLLVMToCVRegMapping()
H A DAArch64InstPrinter.cpp1184 case AArch64::Q5: Reg = AArch64::Q6; break; in getNextVectorRegister()
1185 case AArch64::Q6: Reg = AArch64::Q7; break; in getNextVectorRegister()
/netbsd/external/bsd/iscsi/dist/doc/
H A DFAQ150 Q6. What initiators work with the NetBSD iSCSI target?
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp97 SP::Q6, SP::Q14, ~0U, ~0U,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td274 def Q6 : Rq<24, "F24", [D12, D13]>;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp321 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
674 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,

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