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Searched refs:R600RegisterInfo (Results 1 – 19 of 19) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp24 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { in getSubRegFromChannel()
36 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs()
70 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs( in getCalleeSavedRegs()
75 Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const { in getFrameRegister()
79 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { in getHWRegChan()
83 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { in getHWRegIndex()
87 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( in getCFGStructurizerRegClass()
95 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(Register Reg) const { in isPhysRegLiveAcrossClauses()
108 void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, in eliminateFrameIndex()
115 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { in reserveRegisterTuples()
H A DR600ExpandSpecialInstrs.cpp74 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
124 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
210 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
215 unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
216 unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
225 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
H A DR600RegisterInfo.h22 struct R600RegisterInfo final : public R600GenRegisterInfo {
23 R600RegisterInfo() : R600GenRegisterInfo(0) {} in R600RegisterInfo() function
H A DR600MachineScheduler.h25 struct R600RegisterInfo;
30 const R600RegisterInfo *TRI = nullptr;
H A DR600InstrInfo.h41 const R600RegisterInfo RI;
71 const R600RegisterInfo &getRegisterInfo() const { in getRegisterInfo()
217 const R600RegisterInfo &TRI) const;
H A DR600FrameLowering.cpp21 const R600RegisterInfo *RI in getFrameIndexReference()
H A DR600.td27 include "R600RegisterInfo.td"
H A DR600Subtarget.h67 const R600RegisterInfo *getRegisterInfo() const override { in getRegisterInfo()
H A DR600AsmPrinter.cpp48 const R600RegisterInfo *RI = STM.getRegisterInfo(); in EmitProgramInfoR600()
H A DR600ControlFlowFinalizer.cpp205 const R600RegisterInfo *TRI = nullptr;
280 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
289 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
H A DCMakeLists.txt112 R600RegisterInfo.cpp
H A DR600EmitClauseMarkers.cpp182 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in canClauseLocalKillFitInClause()
H A DR600Packetizer.cpp53 const R600RegisterInfo &TRI;
H A DR600MachineScheduler.cpp27 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); in initialize()
H A DR600InstrInfo.cpp57 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(I); in copyPhysReg()
1069 const R600RegisterInfo &TRI) const { in reserveIndirectRegisters()
H A DAMDILCFGStructurizer.cpp153 const R600RegisterInfo *TRI = nullptr;
H A DAMDGPUISelDAGToDAG.cpp679 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
690 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
/netbsd/external/apache2/llvm/lib/libLLVMAMDGPUCodeGen/
H A DMakefile82 R600RegisterInfo.cpp \
/netbsd/external/apache2/llvm/dist/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/
H A DBUILD.gn195 "R600RegisterInfo.cpp",