Searched refs:RS480_GART_CACHE_CNTRL (Results 1 – 4 of 4) sorted by relevance
75 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); in rs400_gart_tlb_flush()77 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_gart_tlb_flush()83 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); in rs400_gart_tlb_flush()359 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); in rs400_debugfs_gart_info()
148 #define RS480_GART_CACHE_CNTRL 0x2e macro
821 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()827 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, in radeon_set_igpgart()831 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()837 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); in radeon_set_igpgart()
663 #define RS480_GART_CACHE_CNTRL 0x2e macro