Searched refs:Rcp (Results 1 – 9 of 9) sorted by relevance
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2860 auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad}); in emitReciprocalU64() local
2862 B.buildFMul(S32, Rcp, B.buildFConstant(S32, BitsToFloat(0x5f7ffffc))); in emitReciprocalU64()
2891 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); in legalizeUDIV_UREM64Impl() local
2896 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp); in legalizeUDIV_UREM64Impl()
2897 auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1); in legalizeUDIV_UREM64Impl()
3305 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64}, false) in legalizeFDIV64() local
3309 auto Fma0 = B.buildFMA(S64, NegDivScale0, Rcp, One, Flags); in legalizeFDIV64()
3310 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags); in legalizeFDIV64()
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| H A D | AMDGPUCodeGenPrepare.cpp | 1099 Function *Rcp = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, F32Ty); in expandDivRem32() local
1100 Value *RcpY = Builder.CreateCall(Rcp, {FloatY}); in expandDivRem32()
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| H A D | AMDGPUISelLowering.cpp | 1819 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64() local
1820 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
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| H A D | SIISelLowering.cpp | 8543 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
8545 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
8547 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
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| /netbsd/share/man/tools/ |
| H A D | sp.ignore | 711 Rcp
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| H A D | newsp.errs | 185 Rcp
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| /netbsd/external/apache2/llvm/dist/clang/include/clang/Basic/ |
| H A D | BuiltinsNVPTX.def | 227 // Rcp
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | IntrinsicsNVVM.td | 625 // Rcp
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 822 // Rcp
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