Home
last modified time | relevance | path

Searched refs:SMC_SYSCON_RESET_CNTL (Results 1 – 12 of 12) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_si_smc.c118 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_start_smc()
122 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_start_smc()
134 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) | in amdgpu_si_reset_smc()
136 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_reset_smc()
160 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_is_smc_running()
H A Dsid.h72 #define SMC_SYSCON_RESET_CNTL 0x80000000 macro
/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_si_smc.c120 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc()
124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
136 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc()
138 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
168 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running()
H A Dradeon_ci_smc.c121 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc()
124 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
129 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc()
132 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
H A Dsid.h70 #define SMC_SYSCON_RESET_CNTL 0x80000000 macro
H A Dcikd.h74 #define SMC_SYSCON_RESET_CNTL 0x80000000 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_vegam_smumgr.c114 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in vegam_start_smu_in_protection_mode()
128 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_protection_mode()
149 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in vegam_start_smu_in_protection_mode()
152 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_protection_mode()
173 SMC_SYSCON_RESET_CNTL, in vegam_start_smu_in_non_protection_mode()
187 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in vegam_start_smu_in_non_protection_mode()
H A Damdgpu_polaris10_smumgr.c213 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in polaris10_start_smu_in_protection_mode()
227 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_protection_mode()
248 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in polaris10_start_smu_in_protection_mode()
251 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_protection_mode()
272 SMC_SYSCON_RESET_CNTL, in polaris10_start_smu_in_non_protection_mode()
286 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in polaris10_start_smu_in_non_protection_mode()
H A Damdgpu_fiji_smumgr.c113 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in fiji_start_smu_in_protection_mode()
128 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in fiji_start_smu_in_protection_mode()
181 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in fiji_start_smu_in_non_protection_mode()
196 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in fiji_start_smu_in_non_protection_mode()
H A Damdgpu_tonga_smumgr.c108 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in tonga_start_in_protection_mode()
124 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in tonga_start_in_protection_mode()
174 SMC_SYSCON_RESET_CNTL, rst_reg, 1); in tonga_start_in_non_protection_mode()
190 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in tonga_start_in_non_protection_mode()
H A Damdgpu_iceland_smumgr.c117 SMC_SYSCON_RESET_CNTL, rst_reg, 0); in iceland_start_smc()
125 SMC_SYSCON_RESET_CNTL, in iceland_reset_smc()
H A Damdgpu_ci_smumgr.c1906 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0); in ci_start_smc()
2366 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); in ci_upload_firmware()