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Searched refs:SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK (Results 1 – 8 of 8) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7990 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L macro
H A Dgfx_7_2_sh_mask.h8353 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 macro
H A Dgfx_8_1_sh_mask.h10041 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 macro
H A Dgfx_8_0_sh_mask.h9643 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h15646 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK … macro
H A Dgc_9_1_sh_mask.h16955 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK … macro
H A Dgc_9_2_1_sh_mask.h16830 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK … macro
H A Dgc_10_1_0_sh_mask.h23024 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK … macro