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Searched refs:SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h10080 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 macro
H A Dgfx_8_0_sh_mask.h9682 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h15666 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT … macro
H A Dgc_9_1_sh_mask.h16975 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h16850 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h23044 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT … macro