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Searched refs:SQ_SOP1__ENCODING__SHIFT (Results 1 – 7 of 7) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h9491 #define SQ_SOP1__ENCODING__SHIFT 0x00000017 macro
H A Dgfx_7_2_sh_mask.h13102 #define SQ_SOP1__ENCODING__SHIFT 0x17 macro
H A Dgfx_8_1_sh_mask.h15398 #define SQ_SOP1__ENCODING__SHIFT 0x17 macro
H A Dgfx_8_0_sh_mask.h15000 #define SQ_SOP1__ENCODING__SHIFT 0x17 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h2905 #define SQ_SOP1__ENCODING__SHIFT … macro
H A Dgc_9_1_sh_mask.h2753 #define SQ_SOP1__ENCODING__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h2711 #define SQ_SOP1__ENCODING__SHIFT … macro