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Searched refs:SQ_WAVE_INST_DW1__INST_DW1_MASK (Results 1 – 7 of 7) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h9932 #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffffL macro
H A Dgfx_7_2_sh_mask.h12445 #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff macro
H A Dgfx_8_1_sh_mask.h14713 #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff macro
H A Dgfx_8_0_sh_mask.h14315 #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28509 #define SQ_WAVE_INST_DW1__INST_DW1_MASK … macro
H A Dgc_9_1_sh_mask.h29724 #define SQ_WAVE_INST_DW1__INST_DW1_MASK … macro
H A Dgc_9_2_1_sh_mask.h30052 #define SQ_WAVE_INST_DW1__INST_DW1_MASK … macro