Searched refs:ShOpc (Results 1 – 8 of 8) sorted by relevance
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift() argument 54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift() 58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift() 59 O << getShiftOpcStr(ShOpc); in printRegImmShift() 61 if (ShOpc != ARM_AM::rrx) { in printRegImmShift() 391 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand() local 392 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand() 393 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
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H A D | ARMMCCodeEmitter.cpp | 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp() 247 switch (ShOpc) { in getShiftOp()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 5561 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; in lowerRotate() local 5571 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate() 5580 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 232 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress() local 233 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
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H A D | ARMISelDAGToDAG.cpp | 3184 SDValue ShOpc = in tryV6T2BitfieldExtractOp() local 3187 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp()
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H A D | ARMISelLowering.cpp | 6358 unsigned ShOpc = N->getOpcode(); in Expand64BitShift() local 6374 if (ShOpc == ISD::SRL) { in Expand64BitShift() 6383 } else if (ShOpc == ISD::SRA) in Expand64BitShift()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 6575 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT() local 6585 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT() 6593 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 28471 unsigned ShOpc = ConstantAmt ? Opc : X86OpcV; in LowerShift() local 28472 SDValue R0 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt0)); in LowerShift() 28473 SDValue R1 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt1)); in LowerShift() 28474 SDValue R2 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt2)); in LowerShift() 28475 SDValue R3 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt3)); in LowerShift()
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