| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 607 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg()); in getInstrMapping() local
609 if (ShiftAmtTy.getSizeInBits() == 64 && SrcTy.getSizeInBits() == 32) in getInstrMapping()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.h | 324 LLT HalfTy, LLT ShiftAmtTy);
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 406 EVT ShiftAmtTy = TLI.getShiftAmountTy(NOutVT, DAG.getDataLayout()); in PromoteIntRes_BITCAST() local
409 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy)); in PromoteIntRes_BITCAST()
2944 EVT ShiftAmtTy = getShiftAmountTyForConstant(NVT, TLI, DAG); in ExpandIntRes_ABS() local
2947 DAG.getConstant(NVT.getSizeInBits() - 1, dl, ShiftAmtTy)); in ExpandIntRes_ABS()
3026 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); in ExpandIntRes_FLT_ROUNDS() local
3031 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy)); in ExpandIntRes_FLT_ROUNDS()
3332 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); in ExpandIntRes_MUL() local
3333 if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) { in ExpandIntRes_MUL()
3336 ShiftAmtTy = MVT::i32; in ExpandIntRes_MUL()
3338 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy); in ExpandIntRes_MUL()
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| H A D | TargetLowering.cpp | 1815 EVT ShiftAmtTy = VT; in SimplifyDemandedBits() local
1816 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) in SimplifyDemandedBits()
1817 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL); in SimplifyDemandedBits()
1820 TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy); in SimplifyDemandedBits()
8387 EVT ShiftAmtTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandMULO() local
8388 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy); in expandMULO()
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| H A D | DAGCombiner.cpp | 4205 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType()); in visitSDIVLike() local
4206 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy); in visitSDIVLike()
4208 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy); in visitSDIVLike()
4209 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1); in visitSDIVLike()
4215 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy)); in visitSDIVLike()
22150 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType()); in foldSelectCCToShiftAnd() local
22155 SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); in foldSelectCCToShiftAnd()
22175 SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy); in foldSelectCCToShiftAnd()
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| H A D | LegalizeVectorTypes.cpp | 3793 EVT ShiftAmtTy = TLI.getShiftAmountTy(NInVT, DAG.getDataLayout()); in WidenVecRes_BITCAST() local
3796 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy)); in WidenVecRes_BITCAST()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 4453 LLT ShiftAmtTy = MRI.getType(Amt); in narrowScalarShift() local
4468 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); in narrowScalarShift()
4474 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); in narrowScalarShift()
4480 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); in narrowScalarShift()
4481 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); in narrowScalarShift()
4483 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); in narrowScalarShift()
4523 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); in narrowScalarShift()
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| H A D | CombinerHelper.cpp | 1947 LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(SrcTy); in matchCombineShlOfExtend() local
1948 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_SHL, {SrcTy, ShiftAmtTy}})) in matchCombineShlOfExtend()
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