| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 79 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
100 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';); in getVGPRSpillLaneOrTempRegister()
837 assert(Spill.size() == 1); in emitPrologue()
842 .addImm(Spill[0].Lane) in emitPrologue()
854 assert(Spill.size() == 1); in emitPrologue()
859 .addImm(Spill[0].Lane) in emitPrologue()
1027 assert(Spill.size() == 1); in emitEpilogue()
1029 .addReg(Spill[0].VGPR) in emitEpilogue()
1030 .addImm(Spill[0].Lane); in emitEpilogue()
1053 assert(Spill.size() == 1); in emitEpilogue()
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| H A D | SIMachineFunctionInfo.cpp | 371 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
374 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
375 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
379 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
387 Spill.FullyAllocated = true; in allocateVGPRSpillToAGPR()
415 Spill.FullyAllocated = false; in allocateVGPRSpillToAGPR()
421 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
424 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
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| H A D | SIMachineFunctionInfo.h | 780 void setHasSpilledSGPRs(bool Spill = true) {
781 HasSpilledSGPRs = Spill;
788 void setHasSpilledVGPRs(bool Spill = true) {
789 HasSpilledVGPRs = Spill;
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| H A D | SIRegisterInfo.cpp | 1325 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
1332 Spill.VGPR) in spillSGPR()
1334 .addImm(Spill.Lane) in spillSGPR()
1335 .addReg(Spill.VGPR); in spillSGPR()
1421 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
1424 .addReg(Spill.VGPR) in restoreSGPR()
1425 .addImm(Spill.Lane); in restoreSGPR()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RegAllocBasic.cpp | 232 LiveInterval &Spill = *Intfs[i]; in spillInterferences() local
235 if (!VRM->hasPhys(Spill.reg())) in spillInterferences()
240 Matrix->unassign(Spill); in spillInterferences()
243 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in spillInterferences()
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| H A D | InlineSpiller.cpp | 152 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1020 MachineBasicBlock::iterator Spill = std::next(MI); in insertSpill() local
1021 LIS.InsertMachineInstrRangeInMaps(Spill, MIS.end()); in insertSpill()
1022 for (const MachineInstr &MI : make_range(Spill, MIS.end())) in insertSpill()
1031 if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1) in insertSpill()
1225 SlotIndex Idx = LIS.getInstructionIndex(Spill); in addToMergeableSpills()
1228 MergeableSpills[MIdx].insert(&Spill); in addToMergeableSpills()
1238 SlotIndex Idx = LIS.getInstructionIndex(Spill); in rmFromMergeableSpills()
1241 return MergeableSpills[MIdx].erase(&Spill); in rmFromMergeableSpills()
1330 for (const auto Spill : Spills) { in getVisitOrders() local
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| /netbsd/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| H A D | xray_trampoline_powerpc64_asm.S | 8 # Spill r3-r10, f1-f13, and vsr34-vsr45, which are parameter registers.
149 # Spill r3-r4, f1-f8, and vsr34-vsr41, which are return registers.
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | FunctionLoweringInfo.h | 101 Spill, enumerator
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | StatepointLowering.cpp | 176 if (Record.type != RecordType::Spill) in findPreviousSpillSlot()
924 Record.type = RecordType::Spill; in LowerAsSTATEPOINT()
1215 if (Record.type == RecordType::Spill) { in visitGCRelocate()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 771 const SpillLoc &Spill = SpillLocs[LocID - NumRegs + 1]; in emitLoc() local
775 Spill.SpillOffset); in emitLoc()
776 unsigned Base = Spill.SpillBase; in emitLoc()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | Target.td | 60 int SpillSize = SS; // Spill slot size in bits.
61 int SpillAlignment = SA; // Spill slot alignment in bits.
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 1056 // Fill/Spill
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| /netbsd/external/apache2/llvm/dist/llvm/docs/ |
| H A D | AMDGPUUsage.rst | 11280 Spill Table
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| /netbsd/external/gpl3/gcc/dist/gcc/ |
| H A D | ChangeLog-2015 | 22655 (assign_hard_rego): Spill memory profitable allocno unless it is
22668 (spill_for): Spill non spilled static chain pseudo last.
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| H A D | ChangeLog-2014 | 43896 Spill all pseudos on the second iteration.
47848 * lra-constraints.c (simplify_operand_subreg): Spill pseudo if
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| H A D | ChangeLog-2013 | 31947 (curr_insn_transform): Spill pseudos reassigned to NO_REGS.
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