Searched refs:Src0Reg (Results 1 – 9 of 9) sorted by relevance
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 4541 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local 4542 if (!Src0Reg) in selectRem() 4600 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local 4601 if (!Src0Reg) in selectMul() 4613 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local 4614 if (!Src0Reg) in selectMul() 4621 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg); in selectMul() 4808 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectSDiv() local 4809 if (!Src0Reg) in selectSDiv() 4813 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2); in selectSDiv() [all …]
|
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 270 unsigned Src0Reg,
|
H A D | AMDGPUInstructionSelector.cpp | 423 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local 444 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) || in selectG_UADDO_USUBO_UADDE_USUBE() 703 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local 730 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT() 744 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || in selectG_INSERT() 750 .addReg(Src0Reg) in selectG_INSERT() 915 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local 920 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) in selectG_INTRINSIC() 2795 Register Src0Reg = MI.getOperand(1).getReg(); in selectG_SHUFFLE_VECTOR() local 2800 if (MRI->getType(DstReg) != V2S16 || MRI->getType(Src0Reg) != V2S16) in selectG_SHUFFLE_VECTOR() [all …]
|
H A D | R600InstrInfo.cpp | 1219 unsigned Src0Reg, in buildDefaultInstruction() argument 1232 .addReg(Src0Reg) // $src0 in buildDefaultInstruction()
|
H A D | AMDGPULegalizerInfo.cpp | 1944 Register Src0Reg = MI.getOperand(1).getReg(); in legalizeFrem() local 1949 auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags); in legalizeFrem() 1952 B.buildFMA(DstReg, Neg, Src1Reg, Src0Reg, Flags); in legalizeFrem()
|
H A D | AMDGPURegisterBankInfo.cpp | 4010 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local 4012 unsigned Src0Size = MRI.getType(Src0Reg).getSizeInBits(); in getInstrMapping()
|
H A D | SIInstrInfo.cpp | 4816 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local 4828 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill); in legalizeOperandsVOP2()
|
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1938 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local 1940 if (!Src0Reg || !Src1Reg) in selectDivRem() 1943 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
|
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | LegalizerHelper.cpp | 3448 Register Src0Reg = MI.getOperand(2).getReg(); in fewerElementsVectorCmp() local 3450 LLT SrcTy = MRI.getType(Src0Reg); in fewerElementsVectorCmp() 6153 Register Src0Reg = MI.getOperand(1).getReg(); in lowerMergeValues() local 6155 LLT SrcTy = MRI.getType(Src0Reg); in lowerMergeValues() 6159 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); in lowerMergeValues() 6288 Register Src0Reg = MI.getOperand(1).getReg(); in lowerShuffleVector() local 6290 LLT Src0Ty = MRI.getType(Src0Reg); in lowerShuffleVector() 6306 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; in lowerShuffleVector() 6325 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); in lowerShuffleVector() 6328 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector()
|