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Searched refs:TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h14322 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa macro
H A Dgfx_8_1_sh_mask.h16802 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa macro
H A Dgfx_8_0_sh_mask.h16222 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h8916 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT macro
H A Dgc_9_1_sh_mask.h10421 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT macro
H A Dgc_9_2_1_sh_mask.h10251 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT macro