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Searched refs:TmpReg (Results 1 – 25 of 39) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp161 unsigned TmpReg) const;
307 unsigned TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass); in instrumentControlFlow() local
310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " "; in instrumentControlFlow()
312 if (TmpReg == 0) in instrumentControlFlow()
315 ReturnInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
317 CallInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow()
384 unsigned TmpReg) const { in insertRegToSPTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
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H A DAArch64FastISel.cpp413 unsigned TmpReg = createResultReg(RC); in materializeFP() local
420 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
4078 Register TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local
4080 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
4084 Op0 = TmpReg; in emitLSL_ri()
4194 Register TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local
4196 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4200 Op0 = TmpReg; in emitLSR_ri()
4299 Register TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local
4301 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitASR_ri()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2788 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2997 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3392 if (!TmpReg) in expandLoadSingleImmToFPR()
3475 if (!TmpReg) in expandLoadDoubleImmToGPR()
3509 if (!TmpReg) in expandLoadDoubleImmToFPR()
3706 if (!TmpReg) in expandMem16Inst()
3783 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3785 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3833 if (!TmpReg) in expandMem9Inst()
4506 if (!TmpReg) in expandUxw()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp153 unsigned TmpReg = createResultReg(ToRC); in copyRegToRegClass() local
156 return TmpReg; in copyRegToRegClass()
1024 SrcReg = TmpReg; in PPCMoveToFPReg()
1120 SrcReg = TmpReg; in SelectIToFP()
1447 Arg = TmpReg; in processCallArgs()
1459 Arg = TmpReg; in processCallArgs()
1772 SrcReg = TmpReg; in SelectRet()
1781 SrcReg = TmpReg; in SelectRet()
2034 TmpReg) in PPCMaterializeFP()
2054 .addReg(TmpReg) in PPCMaterializeFP()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp631 TmpReg = scavengeGPR8(MI); in expand()
642 if (TmpReg) in expand()
643 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
651 if (TmpReg) { in expand()
747 TmpReg = scavengeGPR8(MI); in expand()
759 if (TmpReg) in expand()
760 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
768 if (TmpReg) { in expand()
797 TmpReg = scavengeGPR8(MI); in expand()
808 if (TmpReg) in expand()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp275 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
278 TmpReg) in foldVGPRCopyIntoRegSequence()
288 .addReg(TmpReg, RegState::Kill); in foldVGPRCopyIntoRegSequence()
289 TmpReg = TmpAReg; in foldVGPRCopyIntoRegSequence()
292 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
598 Register TmpReg in runOnMachineFunction() local
602 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg) in runOnMachineFunction()
604 MI.getOperand(1).setReg(TmpReg); in runOnMachineFunction()
H A DSIRegisterInfo.cpp1133 Register TmpReg; in buildSpillLoadStore() local
1208 if (!TmpReg) { in buildSpillLoadStore()
1212 RS->setRegUsed(TmpReg); in buildSpillLoadStore()
1222 SubReg = TmpReg; in buildSpillLoadStore()
1252 if (!IsStore && TmpReg != AMDGPU::NoRegister) { in buildSpillLoadStore()
1255 .addReg(TmpReg, RegState::Kill); in buildSpillLoadStore()
1679 FIOp.setReg(TmpReg); in eliminateFrameIndex()
1682 if ((!FrameReg || !Offset) && TmpReg) { in eliminateFrameIndex()
1694 UseSGPR ? TmpReg in eliminateFrameIndex()
1700 if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR)) in eliminateFrameIndex()
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H A DSILowerI1Copies.cpp697 unsigned TmpReg = createLaneMaskReg(*MF); in lowerCopiesToI1() local
698 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg) in lowerCopiesToI1()
701 MI.getOperand(1).setReg(TmpReg); in lowerCopiesToI1()
702 SrcReg = TmpReg; in lowerCopiesToI1()
H A DSIWholeQuadMode.cpp914 Register TmpReg; in lowerKillI1() local
941 TmpReg = MRI->createVirtualRegister(TRI->getBoolRC()); in lowerKillI1()
943 BuildMI(MBB, MI, DL, TII->get(XorOpc), TmpReg).add(Op).addReg(Exec); in lowerKillI1()
946 .addReg(TmpReg); in lowerKillI1()
1007 if (TmpReg) in lowerKillI1()
1008 LIS->createAndComputeVirtRegInterval(TmpReg); in lowerKillI1()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp287 Register TmpReg = in ExpandFPMLxInstruction() local
290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DThumbRegisterInfo.cpp512 Register TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
516 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
519 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
523 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
528 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
H A DThumb1FrameLowering.cpp585 unsigned &TmpReg) { in findTemporariesForLR() argument
586 PopReg = TmpReg = 0; in findTemporariesForLR()
592 TmpReg = 0; in findTemporariesForLR()
597 TmpReg = Reg; in findTemporariesForLR()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp1535 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local
1546 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP()
1556 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local
1561 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP()
1565 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP()
1663 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local
1698 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr()
1729 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr()
1752 BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHRX64rr), TmpReg) in hardenLoadAddr()
1765 AddrRegToHardenedReg[Op->getReg()] = TmpReg; in hardenLoadAddr()
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H A DX86CmovConversion.cpp758 Register TmpReg = MRI->createVirtualRegister(RC); in convertCmovInstsToBranches() local
761 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg, in convertCmovInstsToBranches()
803 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg; in convertCmovInstsToBranches()
H A DX86FlagsCopyLowering.cpp834 Register TmpReg = MRI->createVirtualRegister(PromoteRC); in rewriteArithmetic() local
837 .addDef(TmpReg, RegState::Dead) in rewriteArithmetic()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp179 Register TmpReg = I->getParent()->getOperand(0).getReg(); in processCandidate() local
180 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp339 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument
362 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
364 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
366 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h1014 Register TmpReg; in lookThroughCopyInstrs() local
1015 while (mi_match(Reg, MRI, m_Copy(m_Reg(TmpReg)))) { in lookThroughCopyInstrs()
1016 if (MRI.getType(TmpReg).isValid()) in lookThroughCopyInstrs()
1017 Reg = TmpReg; in lookThroughCopyInstrs()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp376 Register TmpReg = VE::SX16; in copyPhysReg() local
377 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); in copyPhysReg()
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
386 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); in copyPhysReg()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp763 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
772 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
777 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
778 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
H A DMipsTargetStreamer.h163 int64_t Offset, unsigned TmpReg, SMLoc IDLoc,
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp226 Register TmpReg = FromReg; in isRevCopyChain() local
228 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI); in isRevCopyChain()
232 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain()
234 if (TmpReg == ToReg) in isRevCopyChain()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp105 void emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
2231 void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg, in emitAuipcInstPair() argument
2246 Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
2254 .addOperand(TmpReg) in emitAuipcInstPair()
2339 MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); in emitLoadStoreSymbol() local
2341 emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_RISCV_PCREL_HI, in emitLoadStoreSymbol()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp426 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon86093a6d0111::X86AsmParser::IntelExprStateMachine
451 TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0), in IntelExprStateMachine()
656 BaseReg = TmpReg; in onPlus()
662 IndexReg = TmpReg; in onPlus()
717 BaseReg = TmpReg; in onMinus()
723 IndexReg = TmpReg; in onMinus()
774 TmpReg = Reg; in onRegister()
868 IndexReg = TmpReg; in onInteger()
965 BaseReg = TmpReg; in onRBrac()
968 IndexReg = TmpReg; in onRBrac()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp905 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO); in narrowScalar()
906 MIRBuilder.buildAnyExt(DstReg, TmpReg); in narrowScalar()
924 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
933 MIRBuilder.buildZExt(DstReg, TmpReg); in narrowScalar()
935 MIRBuilder.buildSExt(DstReg, TmpReg); in narrowScalar()
957 MIRBuilder.buildTrunc(TmpReg, SrcReg); in narrowScalar()
2784 Register TmpReg = in lowerLoad() local
2786 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in lowerLoad()
2791 MIRBuilder.buildAnyExtOrTrunc(DstReg, TmpReg); in lowerLoad()
2794 MIRBuilder.buildSExt(DstReg, TmpReg); in lowerLoad()
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