| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 2833 ISD = ISD::UMIN; in getTypeBasedIntrinsicInstrCost()
3797 {ISD::UMIN, MVT::v16i8, 1}, in getMinMaxCost()
3802 {ISD::UMIN, MVT::v4i32, 1}, in getMinMaxCost()
3803 {ISD::UMIN, MVT::v8i16, 1}, in getMinMaxCost()
3815 {ISD::UMIN, MVT::v8i32, 3}, in getMinMaxCost()
3817 {ISD::UMIN, MVT::v16i16, 3}, in getMinMaxCost()
3819 {ISD::UMIN, MVT::v32i8, 3}, in getMinMaxCost()
3824 {ISD::UMIN, MVT::v8i32, 1}, in getMinMaxCost()
3826 {ISD::UMIN, MVT::v16i16, 1}, in getMinMaxCost()
3955 {ISD::UMIN, MVT::v32i8, 8}, in getMinMaxReductionCost()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 618 UMIN, enumerator
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| /netbsd/external/gpl3/gcc/dist/gcc/config/i386/ |
| H A D | i386-features.c | 587 || GET_CODE (src) == UMIN) in compute_convert_gain()
1004 case UMIN: in convert_insn()
1388 case UMIN: in general_scalar_to_vector_candidate_p()
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| H A D | i386-features.cc | 599 case UMIN: in compute_convert_gain()
1038 case UMIN: in convert_insn()
1450 case UMIN: in general_scalar_to_vector_candidate_p()
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| /netbsd/external/gpl3/gcc.old/dist/gcc/config/i386/ |
| H A D | i386-features.c | 587 || GET_CODE (src) == UMIN) in compute_convert_gain()
1004 case UMIN: in convert_insn()
1388 case UMIN: in general_scalar_to_vector_candidate_p()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 441 case ISD::UMIN: in LegalizeOp()
827 case ISD::UMIN: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 84 case ISD::UMIN: in PromoteIntegerResult()
795 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax); in PromoteIntRes_ADDSUBSHLSAT()
895 return DAG.getNode(ISD::UMIN, dl, VT, V, in SaturateWidenedDIVFIX()
2151 case ISD::UMIN: in ExpandIntegerResult()
2512 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
2513 case ISD::UMIN: in getExpandedMinMaxOps()
2514 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
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| H A D | SelectionDAGDumper.cpp | 272 case ISD::UMIN: return "umin"; in getOperationName()
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| H A D | TargetLowering.cpp | 1743 case ISD::UMIN: { in SimplifyDemandedBits()
7130 isOperationLegal(ISD::UMIN, VT)) { in expandABS()
7132 Result = DAG.getNode(ISD::UMIN, dl, VT, Op, in expandABS()
7794 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, Sub); in clampDynamicVectorIndex()
7801 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, in clampDynamicVectorIndex()
7921 if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && in expandIntMINMAX()
7941 case ISD::UMIN: CC = ISD::SETULT; break; in expandIntMINMAX()
7970 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat()
7972 SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS); in expandAddSubSat()
8771 TrailingBytes = DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, VLBytes); in expandVectorSplice()
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| /netbsd/external/gpl3/gcc/dist/gcc/ |
| H A D | rtlanal.c | 4381 case UMIN: in nonzero_bits_binary_arith_p()
4658 case UMIN: case UMAX: case SMIN: case SMAX: in nonzero_bits1()
4939 case UMIN: in num_sign_bit_copies_binary_arith_p()
5201 case SMIN: case SMAX: case UMIN: case UMAX: in num_sign_bit_copies1()
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| H A D | rtlanal.cc | 4716 case UMIN: in nonzero_bits_binary_arith_p()
4993 case UMIN: case UMAX: case SMIN: case SMAX: in nonzero_bits1()
5280 case UMIN: in num_sign_bit_copies_binary_arith_p()
5542 case SMIN: case SMAX: case UMIN: case UMAX: in num_sign_bit_copies1()
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| H A D | optabs.def | 153 OPTAB_NL(umin_optab, "umin$I$a3", UMIN, "umin", '3', gen_int_libfunc)
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| H A D | print-rtl.c | 1364 case UMIN: in print_exp()
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| /netbsd/external/gpl3/gcc.old/dist/gcc/ |
| H A D | rtlanal.c | 4381 case UMIN: in nonzero_bits_binary_arith_p()
4658 case UMIN: case UMAX: case SMIN: case SMAX: in nonzero_bits1()
4939 case UMIN: in num_sign_bit_copies_binary_arith_p()
5201 case SMIN: case SMAX: case UMIN: case UMAX: in num_sign_bit_copies1()
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| H A D | optabs.def | 153 OPTAB_NL(umin_optab, "umin$I$a3", UMIN, "umin", '3', gen_int_libfunc)
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| H A D | print-rtl.c | 1364 case UMIN: in print_exp()
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| /netbsd/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
| H A D | constraints.md | 510 and UMIN operations."
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| H A D | predicates.md | 717 ;; Used for SVE UMAX and UMIN.
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 108 setOperationAction(ISD::UMIN, T, Legal); in initializeHVXLowering()
197 setOperationAction(ISD::UMIN, T, Custom); in initializeHVXLowering()
2085 case ISD::UMIN: in LowerHvxOperation()
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| /netbsd/external/gpl3/gcc/dist/gcc/config/aarch64/ |
| H A D | constraints.md | 526 and UMIN operations."
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| H A D | predicates.md | 730 ;; Used for SVE UMAX and UMIN.
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| /netbsd/external/gpl3/gcc.old/dist/gcc/config/rl78/ |
| H A D | rl78.md | 744 "rl78_emit_libcall (\"__umindi3\", UMIN, DImode, DImode, 3, operands);
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| /netbsd/external/gpl3/gcc/dist/gcc/config/rl78/ |
| H A D | rl78.md | 744 "rl78_emit_libcall (\"__umindi3\", UMIN, DImode, DImode, 3, operands);
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| /netbsd/external/gpl3/gcc.old/dist/gcc/config/cris/ |
| H A D | cris.md | 2083 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
2136 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2194 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2244 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2306 && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2386 && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleP5600.td | 636 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
|