1 //===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
11 #define LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
12 
13 // Operand Flags
14 #define MO_FLAG_CLAMP (1 << 0)
15 #define MO_FLAG_NEG   (1 << 1)
16 #define MO_FLAG_ABS   (1 << 2)
17 #define MO_FLAG_MASK  (1 << 3)
18 #define MO_FLAG_PUSH  (1 << 4)
19 #define MO_FLAG_NOT_LAST  (1 << 5)
20 #define MO_FLAG_LAST  (1 << 6)
21 #define NUM_MO_FLAGS 7
22 
23 /// Helper for getting the operand index for the instruction flags
24 /// operand.
25 #define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
26 
27 namespace R600_InstFlag {
28   enum TIF {
29     TRANS_ONLY = (1 << 0),
30     TEX = (1 << 1),
31     REDUCTION = (1 << 2),
32     FC = (1 << 3),
33     TRIG = (1 << 4),
34     OP3 = (1 << 5),
35     VECTOR = (1 << 6),
36     //FlagOperand bits 7, 8
37     NATIVE_OPERANDS = (1 << 9),
38     OP1 = (1 << 10),
39     OP2 = (1 << 11),
40     VTX_INST  = (1 << 12),
41     TEX_INST = (1 << 13),
42     ALU_INST = (1 << 14),
43     LDS_1A = (1 << 15),
44     LDS_1A1D = (1 << 16),
45     IS_EXPORT = (1 << 17),
46     LDS_1A2D = (1 << 18)
47   };
48 }
49 
50 #define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
51 
52 /// Defines for extracting register information from register encoding
53 #define HW_REG_MASK 0x1ff
54 #define HW_CHAN_SHIFT 9
55 
56 #define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
57 #define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
58 
59 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
60 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
61 
62 namespace OpName {
63 
64   enum VecOps {
65     UPDATE_EXEC_MASK_X,
66     UPDATE_PREDICATE_X,
67     WRITE_X,
68     OMOD_X,
69     DST_REL_X,
70     CLAMP_X,
71     SRC0_X,
72     SRC0_NEG_X,
73     SRC0_REL_X,
74     SRC0_ABS_X,
75     SRC0_SEL_X,
76     SRC1_X,
77     SRC1_NEG_X,
78     SRC1_REL_X,
79     SRC1_ABS_X,
80     SRC1_SEL_X,
81     PRED_SEL_X,
82     UPDATE_EXEC_MASK_Y,
83     UPDATE_PREDICATE_Y,
84     WRITE_Y,
85     OMOD_Y,
86     DST_REL_Y,
87     CLAMP_Y,
88     SRC0_Y,
89     SRC0_NEG_Y,
90     SRC0_REL_Y,
91     SRC0_ABS_Y,
92     SRC0_SEL_Y,
93     SRC1_Y,
94     SRC1_NEG_Y,
95     SRC1_REL_Y,
96     SRC1_ABS_Y,
97     SRC1_SEL_Y,
98     PRED_SEL_Y,
99     UPDATE_EXEC_MASK_Z,
100     UPDATE_PREDICATE_Z,
101     WRITE_Z,
102     OMOD_Z,
103     DST_REL_Z,
104     CLAMP_Z,
105     SRC0_Z,
106     SRC0_NEG_Z,
107     SRC0_REL_Z,
108     SRC0_ABS_Z,
109     SRC0_SEL_Z,
110     SRC1_Z,
111     SRC1_NEG_Z,
112     SRC1_REL_Z,
113     SRC1_ABS_Z,
114     SRC1_SEL_Z,
115     PRED_SEL_Z,
116     UPDATE_EXEC_MASK_W,
117     UPDATE_PREDICATE_W,
118     WRITE_W,
119     OMOD_W,
120     DST_REL_W,
121     CLAMP_W,
122     SRC0_W,
123     SRC0_NEG_W,
124     SRC0_REL_W,
125     SRC0_ABS_W,
126     SRC0_SEL_W,
127     SRC1_W,
128     SRC1_NEG_W,
129     SRC1_REL_W,
130     SRC1_ABS_W,
131     SRC1_SEL_W,
132     PRED_SEL_W,
133     IMM_0,
134     IMM_1,
135     VEC_COUNT
136  };
137 
138 }
139 
140 //===----------------------------------------------------------------------===//
141 // Config register definitions
142 //===----------------------------------------------------------------------===//
143 
144 #define R_02880C_DB_SHADER_CONTROL                    0x02880C
145 #define   S_02880C_KILL_ENABLE(x)                      (((x) & 0x1) << 6)
146 
147 // These fields are the same for all shader types and families.
148 #define   S_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
149 #define   S_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
150 //===----------------------------------------------------------------------===//
151 // R600, R700 Registers
152 //===----------------------------------------------------------------------===//
153 
154 #define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
155 #define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
156 
157 //===----------------------------------------------------------------------===//
158 // Evergreen, Northern Islands Registers
159 //===----------------------------------------------------------------------===//
160 
161 #define R_028844_SQ_PGM_RESOURCES_PS                 0x028844
162 #define R_028860_SQ_PGM_RESOURCES_VS                 0x028860
163 #define R_028878_SQ_PGM_RESOURCES_GS                 0x028878
164 #define R_0288D4_SQ_PGM_RESOURCES_LS                 0x0288d4
165 
166 #define R_0288E8_SQ_LDS_ALLOC                        0x0288E8
167 
168 #endif
169