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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 28) sorted by relevance

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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1149 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1150 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1151 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
1152 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
1153 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
1154 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
1156 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
1157 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
1158 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
1170 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
[all …]
H A DARMISelLowering.cpp184 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
261 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
440 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
980 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in ARMTargetLowering()
9891 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
16979 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h557 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1483 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1528 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp146 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
177 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
1254 case ISD::VECTOR_SHUFFLE: in LowerOperation()
2240 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp81 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
82 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
136 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
191 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
H A DHexagonISelLowering.cpp1649 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1751 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1752 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1753 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
3143 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAG.cpp910 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp290 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DDAGCombiner.cpp1715 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
18624 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
18658 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
21244 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21245 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
21262 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21263 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21318 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
21319 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
21320 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
[all …]
H A DSelectionDAG.cpp740 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
1918 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
2531 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2619 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
2812 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
3724 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
6034 case ISD::VECTOR_SHUFFLE: in getNode()
H A DLegalizeVectorTypes.cpp66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
950 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
2997 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
H A DLegalizeDAG.cpp2998 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
4571 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
H A DTargetLowering.cpp840 case ISD::VECTOR_SHUFFLE: { in SimplifyMultipleUseDemandedBits()
1127 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedBits()
2703 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedVectorElts()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp352 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
645 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in SystemZTargetLowering()
4649 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
5467 case ISD::VECTOR_SHUFFLE: in LowerOperation()
5738 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
6083 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && in combineSTORE()
6711 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); in PerformDAGCombine()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp765 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
766 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
841 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
994 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal); in PPCTargetLowering()
1042 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal); in PPCTargetLowering()
1328 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in PPCTargetLowering()
10834 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
14471 if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in combineVectorShuffle()
14472 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) { in combineVectorShuffle()
14721 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp334 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
335 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
336 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
693 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom); in SITargetLowering()
694 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in SITargetLowering()
4510 case ISD::VECTOR_SHUFFLE: in LowerOperation()
H A DAMDGPUISelLowering.cpp452 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
488 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1803 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp351 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
467 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td326 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
H A DX86ISelLowering.cpp990 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
997 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1417 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1502 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1730 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2005 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in X86TargetLowering()
7534 case ISD::VECTOR_SHUFFLE: { in getFauxShuffleMask()
10388 isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) { in LowerBUILD_VECTOR()
38088 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in isAddSubOrSubAdd()
38141 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in combineShuffleToFMAddSub()
[all …]
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp673 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in RISCVTargetLowering()
749 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in RISCVTargetLowering()
2314 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td662 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand); in NVPTXTargetLowering()

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