Home
last modified time | relevance | path

Searched refs:VID_UPPER_GPIO_CNTL (Results 1 – 4 of 4) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv6xxd.h118 #define VID_UPPER_GPIO_CNTL 0x740 macro
H A Dradeon_rv6xx_dpm.c739 WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
741 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
744 WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
746 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
781 WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_lowest_entry()
783 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_lowest_entry()
H A Dradeon_r600_dpm.c543 tmp = RREG32(VID_UPPER_GPIO_CNTL); in r600_voltage_control_program_voltages()
545 WREG32(VID_UPPER_GPIO_CNTL, tmp); in r600_voltage_control_program_voltages()
H A Dr600d.h1421 #define VID_UPPER_GPIO_CNTL 0x740 macro