Searched refs:VR4122_MDSIUINT_REG_W (Results 1 – 2 of 2) sorted by relevance
199 #define VR4122_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */ macro209 #define MDSIUINT_REG_W VR4122_MDSIUINT_REG_W
75 VR4122_DSIUINT_REG_W,VR4122_MDSIUINT_REG_W },