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Searched refs:VR4122_MFIRINT_REG_W (Results 1 – 2 of 2) sorted by relevance

/netbsd/sys/arch/hpcmips/vr/
H A Dicureg.h343 #define VR4122_MFIRINT_REG_W 0x02a /* Level2 Mask FIR intr reg */ macro
353 #define MFIRINT_REG_W VR4122_MFIRINT_REG_W
H A Dvr4122ip.c71 VR4122_FIRINT_REG_W,VR4122_MFIRINT_REG_W },