| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.cpp | 27 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
30 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
32 if (VRegs.size() > 0) in lowerReturn()
41 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
47 return VRegs.empty(); in lowerFormalArguments()
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| H A D | PPCCallLowering.h | 30 ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
33 ArrayRef<ArrayRef<Register>> VRegs,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | SwiftErrorValueTracking.cpp | 181 SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs; in propagateVRegs() local
186 VRegs.push_back(std::make_pair( in propagateVRegs()
204 VRegs.size() >= 1 && in propagateVRegs()
206 VRegs, in propagateVRegs()
208 -> bool { return V.second != VRegs[0].second; }) != in propagateVRegs()
209 VRegs.end(); in propagateVRegs()
214 assert(!VRegs.empty() && in propagateVRegs()
217 setCurrentVReg(MBB, SwiftErrorVal, VRegs[0].second); in propagateVRegs()
229 assert(!VRegs.empty() && in propagateVRegs()
234 .addReg(VRegs[0].second); in propagateVRegs()
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| H A D | MIRVRegNamerUtils.cpp | 38 VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) { in getVRegRenameMap() argument
50 for (const auto &VReg : VRegs) { in getVRegRenameMap()
146 std::vector<NamedVReg> VRegs; in renameInstsInMBB() local
159 VRegs.push_back( in renameInstsInMBB()
163 return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false; in renameInstsInMBB()
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| H A D | MIRVRegNamerUtils.h | 65 getVRegRenameMap(const std::vector<NamedVReg> &VRegs);
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| H A D | MachineVerifier.cpp | 2430 SmallVector<Register, 0> VRegs; member in __anon0eafccc60411::FilteringVRegSet
2443 return Filter.filterAndAdd(RS, VRegs); in add()
2447 const_iterator end() const { return VRegs.end(); } in end()
2448 size_t size() const { return VRegs.size(); } in size()
2462 FilteringVRegSet VRegs; in calcRegsPassed() local
2466 VRegs.addToFilter(Info.regsKilled); in calcRegsPassed()
2467 VRegs.addToFilter(Info.regsLiveOut); in calcRegsPassed()
2473 VRegs.add(PredInfo.regsLiveOut); in calcRegsPassed()
2474 VRegs.add(PredInfo.vregsPassed); in calcRegsPassed()
2476 Info.vregsPassed.reserve(VRegs.size()); in calcRegsPassed()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 43 for (unsigned i = 0; i < VRegs.size(); ++i) in assignVRegs()
50 SmallVectorImpl<Register> &VRegs) { in setLeastSignificantFirst() argument
52 std::reverse(VRegs.begin(), VRegs.end()); in setLeastSignificantFirst()
57 SmallVector<Register, 4> VRegs; in handle() local
72 VRegs.clear(); in handle()
208 setLeastSignificantFirst(VRegs); in handleSplit()
209 MIRBuilder.buildMerge(ArgsReg, VRegs); in handleSplit()
317 MIRBuilder.buildUnmerge(VRegs, ArgsReg); in handleSplit()
318 setLeastSignificantFirst(VRegs); in handleSplit()
386 if (!VRegs.empty()) { in lowerReturn()
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| H A D | MipsCallLowering.h | 38 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs,
41 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs);
58 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs,
67 ArrayRef<Register> VRegs,
71 ArrayRef<ArrayRef<Register>> VRegs,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.h | 38 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
44 ArrayRef<Register> VRegs,
48 ArrayRef<ArrayRef<Register>> VRegs) const;
51 ArrayRef<ArrayRef<Register>> VRegs,
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| H A D | AMDGPUCallLowering.cpp | 300 assert(VRegs.size() == SplitEVTs.size() && in lowerReturnVal()
307 Register Reg = VRegs[i]; in lowerReturnVal()
382 else if (!lowerReturnVal(B, Val, VRegs, Ret)) in lowerReturn()
489 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArgumentsKernel()
535 assert(VRegs[i].size() == 1 && in lowerFormalArgumentsKernel()
544 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
547 ArrayRef<Register> OrigArgRegs = VRegs[i]; in lowerFormalArgumentsKernel()
575 return lowerFormalArgumentsKernel(B, F, VRegs); in lowerFormalArguments()
644 for (int I = 0, E = VRegs[Idx].size(); I != E; ++I) in lowerFormalArguments()
645 B.buildUndef(VRegs[Idx][I]); in lowerFormalArguments()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.h | 36 ArrayRef<Register> VRegs,
40 ArrayRef<ArrayRef<Register>> VRegs,
48 ArrayRef<Register> VRegs,
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| H A D | ARMCallLowering.cpp | 179 const Value *Val, ArrayRef<Register> VRegs, in lowerReturnVal() argument
193 ArgInfo OrigRetInfo(VRegs, Val->getType()); in lowerReturnVal()
210 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
212 assert(!Val == VRegs.empty() && "Return value without a vreg"); in lowerReturn()
218 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret)) in lowerReturn()
363 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
398 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 134 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
136 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
140 if (!VRegs.empty()) { in lowerReturn()
146 ArgInfo OrigRetInfo(VRegs, Val->getType()); in lowerReturn()
240 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
262 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1) in lowerFormalArguments()
265 ArgInfo OrigArg(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
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| H A D | X86CallLowering.h | 32 ArrayRef<Register> VRegs,
36 ArrayRef<ArrayRef<Register>> VRegs,
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 436 ArrayRef<Register> VRegs, Register DemoteReg,
442 ArrayRef<Register> VRegs, Register DemoteReg) const;
494 ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI, in lowerReturn() argument
498 return lowerReturn(MIRBuilder, Val, VRegs, FLI); in lowerReturn()
506 ArrayRef<Register> VRegs, in lowerReturn() argument
527 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
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| H A D | LegalizerHelper.h | 184 SmallVectorImpl<Register> &VRegs);
189 SmallVectorImpl<Register> &VRegs,
234 SmallVectorImpl<Register> &VRegs,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVCallLowering.h | 31 ArrayRef<Register> VRegs,
35 ArrayRef<ArrayRef<Register>> VRegs,
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| H A D | RISCVCallLowering.cpp | 25 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
39 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments() argument
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.h | 37 ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
43 ArrayRef<ArrayRef<Register>> VRegs,
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| H A D | AArch64CallLowering.cpp | 341 ArrayRef<Register> VRegs, in lowerReturn() argument
345 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
349 if (!VRegs.empty()) { in lowerReturn()
362 assert(VRegs.size() == SplitEVTs.size() && in lowerReturn()
374 Register CurVReg = VRegs[i]; in lowerReturn()
526 ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const { in lowerFormalArguments() argument
538 ArgInfo OrigArg{VRegs[i], Arg}; in lowerFormalArguments()
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| H A D | AArch64LegalizerInfo.cpp | 803 SmallVectorImpl<Register> &VRegs) { in extractParts() argument
805 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); in extractParts()
806 MIRBuilder.buildUnmerge(VRegs, Reg); in extractParts()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 195 auto *VRegs = VMap.getVRegs(Val); in getOrCreateVRegs() local
208 return *VRegs; in getOrCreateVRegs()
229 return *VRegs; in getOrCreateVRegs()
233 return *VRegs; in getOrCreateVRegs()
348 ArrayRef<Register> VRegs; in translateRet() local
350 VRegs = getOrCreateVRegs(*Ret); in translateRet()
1762 SmallVector<llvm::SrcOp, 4> VRegs; in translateSimpleIntrinsic() local
1805 SmallVector<llvm::SrcOp, 4> VRegs; in translateConstrainedFPIntrinsic() local
2328 if (VRegs.size() > 1) in translateCall()
2330 MIB.addUse(VRegs[0]); in translateCall()
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| H A D | CallLowering.cpp | 766 ArrayRef<Register> VRegs, Register DemoteReg, in insertSRetLoads() argument
776 assert(VRegs.size() == SplitVTs.size()); in insertSRetLoads()
789 MRI.getType(VRegs[I]).getSizeInBytes(), in insertSRetLoads()
791 MIRBuilder.buildLoad(VRegs[I], Addr, *MMO); in insertSRetLoads()
796 ArrayRef<Register> VRegs, in insertSRetStores() argument
806 assert(VRegs.size() == SplitVTs.size()); in insertSRetStores()
820 MRI.getType(VRegs[I]).getSizeInBytes(), in insertSRetStores()
822 MIRBuilder.buildStore(VRegs[I], Addr, *MMO); in insertSRetStores()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCTargetDesc.h | 167 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 169 SmallVectorImpl<unsigned> &VRegs) const;
|