/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_umc_v6_1.c | 124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count() 130 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_query_correctable_error_count() 135 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count() 141 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_query_correctable_error_count() 339 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel() 341 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_err_cnt_init_per_channel() 346 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel() 347 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_err_cnt_init_per_channel()
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H A D | amdgpu_cik.c | 1563 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable() 1567 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable() 1614 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable() 1669 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm() 1674 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm() 1679 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm() 1692 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm() 1756 WREG32_PCIE(ixPCIE_LC_CNTL2, data); in cik_program_aspm() 1793 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm() 1801 WREG32_PCIE(ixPCIE_CNTL2, data); in cik_program_aspm() [all …]
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H A D | amdgpu_nbio_v6_1.c | 175 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating() 195 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep() 275 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers() 281 WREG32_PCIE(smnPCIE_CI_CNTL, data); in nbio_v6_1_init_registers()
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H A D | amdgpu_nbio_v7_4.c | 224 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_4_update_medium_grain_light_sleep() 510 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); in nbio_v7_4_query_ras_error_count() 514 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, in nbio_v7_4_query_ras_error_count() 520 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); in nbio_v7_4_query_ras_error_count() 524 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); in nbio_v7_4_query_ras_error_count()
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H A D | amdgpu_nbio_v2_3.c | 224 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v2_3_update_medium_grain_clock_gating() 244 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v2_3_update_medium_grain_light_sleep() 324 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v2_3_init_registers()
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H A D | amdgpu_nbio_v7_0.c | 176 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating() 218 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
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H A D | amdgpu_soc15.c | 861 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); in soc15_get_pcie_usage() 867 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in soc15_get_pcie_usage() 876 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in soc15_get_pcie_usage() 910 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); in vega20_get_pcie_usage() 916 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in vega20_get_pcie_usage() 925 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in vega20_get_pcie_usage()
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H A D | amdgpu_si.c | 1381 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in si_get_pcie_usage() 1387 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in si_get_pcie_usage() 1396 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in si_get_pcie_usage() 1899 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm() 2062 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
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H A D | amdgpu_vi.c | 1037 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in vi_get_pcie_usage() 1043 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in vi_get_pcie_usage() 1052 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in vi_get_pcie_usage() 1442 WREG32_PCIE(ixPCIE_CNTL2, data); in vi_update_bif_medium_grain_light_sleep()
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H A D | amdgpu_cgs.c | 101 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
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H A D | amdgpu_debugfs.c | 319 WREG32_PCIE(*pos >> 2, value); in amdgpu_debugfs_regs_pcie_write()
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H A D | amdgpu.h | 1058 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
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H A D | amdgpu_gmc_v7_0.c | 893 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_r300.c | 103 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush() 197 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable() 200 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable() 201 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable() 202 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable() 209 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); in rv370_pcie_gart_enable() 213 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable() 226 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); in rv370_pcie_gart_disable() 227 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); in rv370_pcie_gart_disable() 228 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_disable() [all …]
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H A D | radeon_si.c | 5589 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls() 7313 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm() 7480 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
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H A D | radeon_rv6xx_dpm.c | 140 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
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H A D | radeon_rv770_dpm.c | 131 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
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H A D | radeon.h | 2603 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) macro
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
H A D | amdgpu_smu_v11_0.c | 208 WREG32_PCIE(addr_start, src[i]); in smu_v11_0_load_microcode() 212 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode() 214 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()
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