| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_device.c | 873 &adev->wb.wb_obj, &adev->wb.gpu_addr, in amdgpu_device_wb_init()
2209 adev = gpu_ins->adev; in amdgpu_device_enable_mgpu_fan_boost()
2872 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; in amdgpu_device_get_job_timeout_settings()
2916 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; in amdgpu_device_get_job_timeout_settings()
3054 &adev->rmmiot, &adev->rmmioh, in amdgpu_device_init()
3055 &adev->rmmio_base, &adev->rmmio_size)) in amdgpu_device_init()
3062 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); in amdgpu_device_init()
3075 &adev->rio_memt, &adev->rio_memh, in amdgpu_device_init()
3081 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); in amdgpu_device_init()
3410 bus_space_unmap(adev->rmmiot, adev->rmmioh, adev->rmmio_size); in amdgpu_device_fini()
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| H A D | amdgpu_soc15.c | 277 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
657 return adev->nbio.funcs->get_rev_id(adev); in soc15_get_rev_id()
700 adev->rev_id = soc15_get_rev_id(adev); in soc15_set_ip_blocks()
701 adev->nbio.funcs->detect_hw_virt(adev); in soc15_set_ip_blocks()
823 adev->nbio.funcs->hdp_flush(adev, ring); in soc15_flush_hdp()
1086 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1254 r = adev->nbio.funcs->ras_late_init(adev); in soc15_common_late_init()
1266 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1276 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1294 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in soc15_doorbell_range_init()
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| H A D | amdgpu_gmc_v9_0.c | 627 struct amdgpu_device *adev = ring->adev; in gmc_v9_0_emit_flush_gpu_tlb() local
669 struct amdgpu_device *adev = ring->adev; in gmc_v9_0_emit_pasid_mapping() local
966 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v9_0_mc_init()
977 adev->gmc.aper_tag = adev->pdev->pd_pa.pa_memt; in gmc_v9_0_mc_init()
983 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v9_0_mc_init()
987 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v9_0_mc_init()
1010 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); in gmc_v9_0_mc_init()
1369 adev->nbio.funcs->hdp_flush(adev, NULL); in gmc_v9_0_hw_init()
1387 adev->umc.funcs->init_registers(adev); in gmc_v9_0_hw_init()
1421 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); in gmc_v9_0_hw_fini()
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| H A D | amdgpu_nv.c | 78 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
133 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
475 adev->nbio.funcs->detect_hw_virt(adev); in nv_set_ip_blocks()
537 return adev->nbio.funcs->get_rev_id(adev); in nv_get_rev_id()
542 adev->nbio.funcs->hdp_flush(adev, ring); in nv_flush_hdp()
669 adev->rev_id = nv_get_rev_id(adev); in nv_common_early_init()
692 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
713 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
742 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
791 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
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| H A D | amdgpu_vi.c | 1140 adev->rev_id = vi_get_rev_id(adev); in vi_common_early_init()
1167 adev->external_rev_id = adev->rev_id + 0x3c; in vi_common_early_init()
1184 adev->external_rev_id = adev->rev_id + 0x14; in vi_common_early_init()
1207 adev->external_rev_id = adev->rev_id + 0x5A; in vi_common_early_init()
1230 adev->external_rev_id = adev->rev_id + 0x50; in vi_common_early_init()
1253 adev->external_rev_id = adev->rev_id + 0x64; in vi_common_early_init()
1277 adev->external_rev_id = adev->rev_id + 0x6E; in vi_common_early_init()
1304 adev->external_rev_id = adev->rev_id + 0x1; in vi_common_early_init()
1327 adev->external_rev_id = adev->rev_id + 0x61; in vi_common_early_init()
1767 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
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| H A D | amdgpu_gart.c | 116 bus_dmamap_unload(adev->ddev->dmat, adev->dummy_page_map); in amdgpu_gart_dummy_page_init()
152 bus_dmamap_unload(adev->ddev->dmat, adev->dummy_page_map); in amdgpu_gart_dummy_page_fini()
157 pci_unmap_page(adev->pdev, adev->dummy_page_addr, in amdgpu_gart_dummy_page_fini()
188 r = amdgpu_bo_create(adev, &bp, &adev->gart.bo); in amdgpu_gart_table_vram_alloc()
218 r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr); in amdgpu_gart_table_vram_pin()
274 adev->gart.table_size / adev->gart.num_gpu_pages; in amdgpu_gart_pre_update()
290 adev->gart.table_size / adev->gart.num_gpu_pages; in amdgpu_gart_post_update()
336 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, in amdgpu_gart_unbind()
383 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, in amdgpu_gart_unbind()
518 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, in amdgpu_gart_bind()
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| H A D | amdgpu_gmc_v10_0.c | 351 adev->nbio.funcs->hdp_flush(adev, NULL); in gmc_v10_0_flush_gpu_tlb()
508 struct amdgpu_device *adev = ring->adev; in gmc_v10_0_emit_pasid_mapping() local
656 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_late_init()
666 amdgpu_gmc_vram_location(adev, &adev->gmc, base); in gmc_v10_0_vram_gtt_location()
689 adev->gmc.aper_tag = adev->pdev->pd_pa.pa_memt; in gmc_v10_0_mc_init()
695 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v10_0_mc_init()
696 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v10_0_mc_init()
715 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); in gmc_v10_0_mc_init()
734 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v10_0_gart_init()
940 adev->nbio.funcs->hdp_flush(adev, NULL); in gmc_v10_0_gart_enable()
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| H A D | amdgpu_gfx.c | 137 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); in amdgpu_gfx_scratch_free()
308 ring->adev = NULL; in amdgpu_gfx_kiq_init_ring()
329 amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs); in amdgpu_gfx_kiq_free_ring()
559 if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { in amdgpu_gfx_off_ctrl()
582 if (!adev->gfx.ras_if) in amdgpu_gfx_ras_late_init()
591 r = amdgpu_ras_late_init(adev, adev->gfx.ras_if, in amdgpu_gfx_ras_late_init()
596 if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) { in amdgpu_gfx_ras_late_init()
597 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in amdgpu_gfx_ras_late_init()
608 amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info); in amdgpu_gfx_ras_late_init()
618 adev->gfx.ras_if) { in amdgpu_gfx_ras_fini()
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| H A D | amdgpu_pm.c | 102 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
171 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) in amdgpu_get_dpm_state()
207 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) in amdgpu_set_dpm_state()
311 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) in amdgpu_get_dpm_forced_performance_level()
1467 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_set_pp_sclk_od()
1536 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_set_pp_mclk_od()
3119 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { in amdgpu_dpm_change_power_state_locked()
3123 adev->pm.dpm.state = adev->pm.dpm.user_state; in amdgpu_dpm_change_power_state_locked()
3217 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
3371 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) || in amdgpu_pm_sysfs_init()
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| H A D | amdgpu_dpm.h | 259 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
262 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
265 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
274 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
277 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
283 ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
307 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
319 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
322 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
325 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
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| H A D | amdgpu_acp.c | 105 adev->acp.parent = adev->dev; in acp_sw_init()
128 void *adev; member
139 adev = apd->adev; in acp_poweroff()
160 adev = apd->adev; in acp_poweron()
221 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) in acp_hw_init()
237 adev->acp.acp_genpd->adev = adev; in acp_hw_init()
333 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; in acp_hw_init()
341 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; in acp_hw_init()
342 adev->acp.acp_cell[0].platform_data = &adev->asic_type; in acp_hw_init()
347 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; in acp_hw_init()
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| H A D | amdgpu_irq.c | 162 ret = amdgpu_ih_process(adev, &adev->irq.ih); in amdgpu_irq_handler()
172 if (adev->nbio.funcs && in amdgpu_irq_handler()
174 adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev); in amdgpu_irq_handler()
176 if (adev->nbio.funcs && in amdgpu_irq_handler()
178 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev); in amdgpu_irq_handler()
196 amdgpu_ih_process(adev, &adev->irq.ih1); in amdgpu_irq_handle_ih1()
211 amdgpu_ih_process(adev, &adev->irq.ih2); in amdgpu_irq_handle_ih2()
287 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc); in amdgpu_irq_init()
304 r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0)); in amdgpu_irq_init()
709 if (adev->irq.domain) { in amdgpu_irq_remove_domain()
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| H A D | amdgpu_kv_dpm.c | 1366 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1368 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1379 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1381 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1404 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
2980 adev->powerplay.pp_handle = adev; in kv_dpm_early_init()
3019 adev->pm.default_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3020 adev->pm.default_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3021 adev->pm.current_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3033 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
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| H A D | amdgpu_amdkfd.c | 73 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, in amdgpu_amdkfd_device_probe()
74 adev->pdev, adev->asic_type, vf); in amdgpu_amdkfd_device_probe()
76 if (adev->kfd.dev) in amdgpu_amdkfd_device_probe()
102 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { in amdgpu_doorbell_get_kfd_info()
167 kgd2kfd_device_init(adev->kfd.dev, adev->ddev, &gpu_resources); in amdgpu_amdkfd_device_init()
182 if (adev->kfd.dev) in amdgpu_amdkfd_interrupt()
188 if (adev->kfd.dev) in amdgpu_amdkfd_suspend()
196 if (adev->kfd.dev) in amdgpu_amdkfd_resume()
206 if (adev->kfd.dev) in amdgpu_amdkfd_pre_reset()
216 if (adev->kfd.dev) in amdgpu_amdkfd_post_reset()
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| H A D | amdgpu_cgs.c | 257 if (!adev->pm.fw) { in amdgpu_cgs_get_firmware_info()
339 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || in amdgpu_cgs_get_firmware_info()
340 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || in amdgpu_cgs_get_firmware_info()
341 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) || in amdgpu_cgs_get_firmware_info()
342 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) || in amdgpu_cgs_get_firmware_info()
343 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) { in amdgpu_cgs_get_firmware_info()
350 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) || in amdgpu_cgs_get_firmware_info()
351 ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) { in amdgpu_cgs_get_firmware_info()
445 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); in amdgpu_cgs_get_firmware_info()
455 adev->pm.fw = NULL; in amdgpu_cgs_get_firmware_info()
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| H A D | amdgpu_gmc_v6_0.c | 150 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v6_0_init_microcode()
175 if (!adev->gmc.fw) in gmc_v6_0_mc_load_microcode()
343 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v6_0_mc_init()
344 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v6_0_mc_init()
345 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v6_0_mc_init()
348 adev->gmc.aper_tag = adev->pdev->pd_pa.pa_memt; in gmc_v6_0_mc_init()
369 gmc_v6_0_vram_gtt_location(adev, &adev->gmc); in gmc_v6_0_mc_init()
595 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v6_0_gart_init()
817 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v6_0_late_init()
889 adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev); in gmc_v6_0_sw_init()
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| H A D | amdgpu_rlc.c | 48 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
51 if (adev->cg_flags & in amdgpu_gfx_rlc_enter_safe_mode()
54 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
72 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
75 if (adev->cg_flags & in amdgpu_gfx_rlc_exit_safe_mode()
78 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
107 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_sr()
136 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); in amdgpu_gfx_rlc_init_csb()
144 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_csb()
163 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in amdgpu_gfx_rlc_init_cpt()
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| H A D | amdgpu_xgmi.c | 158 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); in amdgpu_xgmi_show_error()
167 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); in amdgpu_xgmi_show_error()
197 if (adev != hive->adev) { in amdgpu_xgmi_sysfs_add_dev_info()
218 sysfs_remove_link(&adev->dev->kobj, adev->ddev->unique); in amdgpu_xgmi_sysfs_add_dev_info()
233 sysfs_remove_link(&adev->dev->kobj, adev->ddev->unique); in amdgpu_xgmi_sysfs_rem_dev_info()
272 tmp->adev = adev; in amdgpu_get_xgmi_hive()
301 adev->pstate = is_high_pstate ? pstate : adev->pstate; in amdgpu_xgmi_set_pstate()
404 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); in amdgpu_xgmi_add_device()
458 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); in amdgpu_xgmi_add_device()
461 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, in amdgpu_xgmi_add_device()
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| H A D | amdgpu_cik.c | 1970 adev->rev_id = cik_get_rev_id(adev); in cik_common_early_init()
1974 adev->cg_flags = in cik_common_early_init()
1991 adev->pg_flags = 0; in cik_common_early_init()
1992 adev->external_rev_id = adev->rev_id + 0x14; in cik_common_early_init()
1995 adev->cg_flags = in cik_common_early_init()
2011 adev->pg_flags = 0; in cik_common_early_init()
2015 adev->cg_flags = in cik_common_early_init()
2030 adev->pg_flags = in cik_common_early_init()
2051 adev->cg_flags = in cik_common_early_init()
2066 adev->pg_flags = in cik_common_early_init()
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| H A D | amdgpu_vega20_reg_init.c | 34 int vega20_reg_base_init(struct amdgpu_device *adev) in vega20_reg_base_init() argument
63 void vega20_doorbell_index_init(struct amdgpu_device *adev) in vega20_doorbell_index_init() argument
65 adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; in vega20_doorbell_index_init()
66 adev->doorbell_index.mec_ring0 = AMDGPU_VEGA20_DOORBELL_MEC_RING0; in vega20_doorbell_index_init()
67 adev->doorbell_index.mec_ring1 = AMDGPU_VEGA20_DOORBELL_MEC_RING1; in vega20_doorbell_index_init()
68 adev->doorbell_index.mec_ring2 = AMDGPU_VEGA20_DOORBELL_MEC_RING2; in vega20_doorbell_index_init()
69 adev->doorbell_index.mec_ring3 = AMDGPU_VEGA20_DOORBELL_MEC_RING3; in vega20_doorbell_index_init()
70 adev->doorbell_index.mec_ring4 = AMDGPU_VEGA20_DOORBELL_MEC_RING4; in vega20_doorbell_index_init()
71 adev->doorbell_index.mec_ring5 = AMDGPU_VEGA20_DOORBELL_MEC_RING5; in vega20_doorbell_index_init()
85 adev->doorbell_index.ih = AMDGPU_VEGA20_DOORBELL_IH; in vega20_doorbell_index_init()
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| H A D | amdgpu_gfx_v10_0.c | 284 struct amdgpu_device *adev = kiq_ring->adev; in gfx10_kiq_map_queues() local
460 struct amdgpu_device *adev = ring->adev; in gfx_v10_0_ring_test_ring() local
507 struct amdgpu_device *adev = ring->adev; in gfx_v10_0_ring_test_ib() local
1790 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v10_0_init_csb()
1905 adev->gfx.rlc.funcs->stop(adev); in gfx_v10_0_rlc_resume()
1927 adev->gfx.rlc.funcs->start(adev); in gfx_v10_0_rlc_resume()
2631 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v10_0_cp_gfx_load_microcode()
2967 struct amdgpu_device *adev = ring->adev; in gfx_v10_0_kiq_setting() local
2980 struct amdgpu_device *adev = ring->adev; in gfx_v10_0_gfx_mqd_init() local
3068 struct amdgpu_device *adev = ring->adev; in gfx_v10_0_gfx_queue_init_register() local
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| H A D | amdgpu_gmc_v8_0.c | 281 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v8_0_init_microcode()
587 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v8_0_mc_init()
588 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v8_0_mc_init()
591 adev->gmc.aper_tag = adev->pdev->pd_pa.pa_memt; in gmc_v8_0_mc_init()
597 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
602 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v8_0_mc_init()
604 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
627 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); in gmc_v8_0_mc_init()
978 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v8_0_gart_init()
1087 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_late_init()
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| H A D | amdgpu_mxgpu_nv.c | 161 r = xgpu_nv_poll_ack(adev); in xgpu_nv_mailbox_trans_msg()
260 adev->in_gpu_reset = true; in xgpu_nv_mailbox_flr_work()
272 adev->in_gpu_reset = false; in xgpu_nv_mailbox_flr_work()
346 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_nv_mailbox_add_irq_id()
350 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_nv_mailbox_add_irq_id()
352 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_add_irq_id()
363 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
366 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_get_irq()
368 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
379 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_put_irq()
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| H A D | amdgpu_gmc_v7_0.c | 164 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v7_0_init_microcode()
385 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v7_0_mc_init()
386 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v7_0_mc_init()
389 adev->gmc.aper_tag = adev->pdev->pd_pa.pa_memt; in gmc_v7_0_mc_init()
394 adev->gmc.real_vram_size > adev->gmc.aper_size) { in gmc_v7_0_mc_init()
396 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v7_0_mc_init()
401 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v7_0_mc_init()
426 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); in gmc_v7_0_mc_init()
740 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v7_0_gart_init()
975 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v7_0_late_init()
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| H A D | amdgpu_kms.c | 62 if (gpu_instance->adev == adev) { in amdgpu_unregister_gpu_instance()
89 if (adev == NULL) in amdgpu_driver_unload_kms()
100 if (adev->runpm) { in amdgpu_driver_unload_kms()
110 kfree(adev); in amdgpu_driver_unload_kms()
127 gpu_instance->adev = adev; in amdgpu_register_gpu_instance()
154 if (adev == NULL) { in amdgpu_driver_load_kms()
195 if (adev->runpm) { in amdgpu_driver_load_kms()
208 if (adev->rmmio_size && adev->runpm) in amdgpu_driver_load_kms()
1024 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, in amdgpu_driver_open_kms()
1199 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); in amdgpu_enable_vblank_kms()
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