/netbsd/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
H A D | nouveau_nvkm_subdev_clk_base.c | 198 ret = clk->func->calc(clk, cstate); in nvkm_cstate_prog() 200 ret = clk->func->prog(clk); in nvkm_cstate_prog() 201 clk->func->tidy(clk); in nvkm_cstate_prog() 318 clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, in nvkm_pstate_work() 319 clk->astate, clk->temp, clk->dstate); in nvkm_pstate_work() 321 pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; in nvkm_pstate_work() 568 clk->astate = min(clk->astate, clk->state_nr - 1); in nvkm_clk_astate() 587 clk->dstate = min(clk->dstate, clk->state_nr - 1); in nvkm_clk_dstate() 618 clk->func->fini(clk); in nvkm_clk_fini() 646 return clk->func->init(clk); in nvkm_clk_init() [all …]
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H A D | nouveau_nvkm_subdev_clk_mcp77.c | 262 clk->sctrl = P1 << 16; in mcp77_clk_calc() 271 clk->vdiv = divs << 16; in mcp77_clk_calc() 274 clk->vdiv = P1 << 16; in mcp77_clk_calc() 279 clk->ccoef, clk->cpost, clk->cctrl); in mcp77_clk_calc() 281 clk->scoef, clk->spost, clk->sctrl); in mcp77_clk_calc() 323 switch (clk->csrc) { in mcp77_clk_prog() 340 switch (clk->ssrc) { in mcp77_clk_prog() 368 switch (clk->vsrc) { in mcp77_clk_prog() 422 struct mcp77_clk *clk; in mcp77_clk_new() local 424 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in mcp77_clk_new() [all …]
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H A D | nouveau_nvkm_subdev_clk_gm20b.c | 482 gm20b_dvfs_calc_det_coeff(clk, clk->new_uv, &clk->new_dvfs); in gm20b_clk_calc() 584 if (clk->uv == clk->new_uv) in gm20b_clk_prog() 610 if (clk->uv < clk->new_uv) in gm20b_clk_prog() 635 clk->uv = clk->new_uv; in gm20b_clk_prog() 636 clk->dvfs = clk->new_dvfs; in gm20b_clk_prog() 637 clk->base.pll = clk->new_pll; in gm20b_clk_prog() 751 bool fused = clk->uvdet_offs && clk->uvdet_slope; in gm20b_clk_init_dvfs() 799 clk->uvdet_offs, clk->uvdet_slope); in gm20b_clk_init_dvfs() 803 gm20b_dvfs_calc_det_coeff(clk, clk->uv, &clk->dvfs); in gm20b_clk_init_dvfs() 922 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in gm20b_clk_new_speedo0() [all …]
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H A D | nouveau_nvkm_subdev_clk_gt215.c | 104 sclk = read_vco(clk, idx); in read_clk() 199 info->clk = 0; in gt215_clk_info() 203 info->clk = 0x00000100; in gt215_clk_info() 206 info->clk = 0x00002100; in gt215_clk_info() 209 info->clk = 0x00002140; in gt215_clk_info() 283 &clk->eng[dom]); in calc_clk() 297 info->clk = 0; in calc_host() 510 prog_host(clk); in gt215_clk_prog() 547 struct gt215_clk *clk; in gt215_clk_new() local 549 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in gt215_clk_new() [all …]
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H A D | nouveau_nvkm_subdev_clk_gk20a.c | 141 clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl)); in gk20a_pllg_calc_mnp() 149 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { in gk20a_pllg_calc_mnp() 499 ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll); in gk20a_clk_prog() 501 ret = gk20a_pllg_program_mnp(clk, &clk->pll); in gk20a_clk_prog() 633 clk->params = params; in gk20a_clk_ctor() 634 clk->parent_rate = clk_get_rate(tdev->clk); in gk20a_clk_ctor() 649 struct gk20a_clk *clk; in gk20a_clk_new() local 652 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in gk20a_clk_new() 653 if (!clk) in gk20a_clk_new() 655 *pclk = &clk->base; in gk20a_clk_new() [all …]
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H A D | nouveau_nvkm_subdev_clk_gf100.c | 193 return read_clk(clk, 0x00); in gf100_clk_read() 195 return read_clk(clk, 0x01); in gf100_clk_read() 197 return read_clk(clk, 0x02); in gf100_clk_read() 199 return read_clk(clk, 0x07); in gf100_clk_read() 201 return read_clk(clk, 0x08); in gf100_clk_read() 437 if (!clk->eng[j].freq) in gf100_clk_prog() 439 stage[i].exec(clk, j); in gf100_clk_prog() 450 memset(clk->eng, 0x00, sizeof(clk->eng)); in gf100_clk_tidy() 478 struct gf100_clk *clk; in gf100_clk_new() local 480 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in gf100_clk_new() [all …]
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H A D | nouveau_nvkm_subdev_clk_gk104.c | 206 return read_mem(clk); in gk104_clk_read() 208 return read_clk(clk, 0x00); in gk104_clk_read() 210 return read_clk(clk, 0x01); in gk104_clk_read() 212 return read_clk(clk, 0x02); in gk104_clk_read() 214 return read_clk(clk, 0x07); in gk104_clk_read() 474 if (!clk->eng[j].freq) in gk104_clk_prog() 476 stage[i].exec(clk, j); in gk104_clk_prog() 487 memset(clk->eng, 0x00, sizeof(clk->eng)); in gk104_clk_tidy() 514 struct gk104_clk *clk; in gk104_clk_new() local 516 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in gk104_clk_new() [all …]
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H A D | nouveau_nvkm_subdev_clk_nv50.c | 37 read_div(struct nv50_clk *clk) in read_div() argument 159 return read_pll_src(clk, base); in read_pll_ref() 169 u32 ref = read_pll_ref(clk, base); in read_pll() 199 struct nv50_clk *clk = nv50_clk(base); in nv50_clk_read() local 341 pll.refclk = read_pll_ref(clk, reg); in calc_pll() 408 out = read_pll(clk, 0x004030); in nv50_clk_calc() 503 return clk_exec(&clk->hwsq, true); in nv50_clk_prog() 510 clk_exec(&clk->hwsq, false); in nv50_clk_tidy() 517 struct nv50_clk *clk; in nv50_clk_new_() local 520 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in nv50_clk_new_() [all …]
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H A D | nouveau_nvkm_subdev_clk_nv40.c | 87 read_clk(struct nv40_clk *clk, u32 src) in read_clk() argument 91 return read_pll_2(clk, 0x004000); in read_clk() 93 return read_pll_1(clk, 0x004008); in read_clk() 119 return read_pll_2(clk, 0x4020); in nv40_clk_read() 167 clk->npll_coef = (N1 << 8) | M1; in nv40_clk_calc() 181 clk->ctrl = 0x00000223; in nv40_clk_calc() 183 clk->spll = 0x00000000; in nv40_clk_calc() 184 clk->ctrl = 0x00000333; in nv40_clk_calc() 228 struct nv40_clk *clk; in nv40_clk_new() local 230 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) in nv40_clk_new() [all …]
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/netbsd/sys/dev/clk/ |
H A D | clk.c | 91 struct clk *clk; in clk_sysctl_rate_helper() local 107 struct clk *clk, *clk_parent; in clk_sysctl_parent_helper() local 125 struct clk *clk, *clk_parent; in clk_sysctl_parent_domain_helper() local 150 clk_attach(struct clk *clk) in clk_attach() argument 217 clk_put(struct clk *clk) in clk_put() argument 220 clk->domain->funcs->put(clk->domain->priv, clk); in clk_put() 224 clk_get_rate(struct clk *clk) in clk_get_rate() argument 256 clk_enable(struct clk *clk) in clk_enable() argument 259 return clk->domain->funcs->enable(clk->domain->priv, clk); in clk_enable() 265 clk_disable(struct clk *clk) in clk_disable() argument [all …]
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/netbsd/sys/arch/arm/nxp/ |
H A D | imx_ccm.c | 74 if (clk == NULL) in imx_ccm_clock_get() 81 imx_ccm_clock_put(void *priv, struct clk *clk) in imx_ccm_clock_put() argument 93 return clk->get_rate(sc, clk); in imx_ccm_clock_get_rate() 121 return clk->set_rate(sc, clk, rate); in imx_ccm_clock_set_rate() 143 return clk->round_rate(sc, clk, rate); in imx_ccm_clock_round_rate() 163 if (clk->enable) in imx_ccm_clock_enable() 164 error = clk->enable(sc, clk, 1); in imx_ccm_clock_enable() 177 error = clk->enable(sc, clk, 0); in imx_ccm_clock_disable() 192 return clk->set_parent(sc, clk, clkp_parent->name); in imx_ccm_clock_set_parent() 206 parent = clk->get_parent(sc, clk); in imx_ccm_clock_get_parent() [all …]
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H A D | imx6_ccm.c | 98 struct clk *clk = &imx6_clks[n].base; in imx6ccm_attach_common() local 99 struct clk *clk_parent = clk_get_parent(clk); in imx6ccm_attach_common() 107 struct clk * 137 struct clk *clk; in imxccm_init_clocks() local 153 clk_put(clk); in imxccm_init_clocks() 474 imxccm_clk_put(void *priv, struct clk *clk) in imxccm_clk_put() argument 484 imxccm_clk_get_rate(void *priv, struct clk *clk) in imxccm_clk_get_rate() argument 592 imxccm_clk_enable(void *priv, struct clk *clk) in imxccm_clk_enable() argument 619 imxccm_clk_disable(void *priv, struct clk *clk) in imxccm_clk_disable() argument 642 imxccm_clk_set_parent(void *priv, struct clk *clk, struct clk *parent) in imxccm_clk_set_parent() argument [all …]
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/netbsd/sys/arch/arm/altera/ |
H A D | cycv_clkmgr.c | 43 static struct clk *cycv_clkmgr_clock_get_parent(void *, struct clk *); 57 struct clk base; 239 clk->refcnt = 0; in cycv_clkmgr_clock_parse() 376 clk->id, cycv_clkmgr_clock_get_rate(sc, &clk->base)); in cycv_clkmgr_clock_print() 397 tmp = (tmp & clk->u.div.mask) >> clk->u.div.shift; in cycv_clkmgr_clock_print() 432 return clk == NULL? NULL : &clk->base; in cycv_clkmgr_clock_decode() 446 cycv_clkmgr_clock_put(void *priv, struct clk *clk) in cycv_clkmgr_clock_put() argument 488 divisor = (divisor & clk->u.div.mask) >> clk->u.div.shift; in cycv_clkmgr_clock_get_rate() 536 cycv_clkmgr_clock_enable(void *priv, struct clk *clk) in cycv_clkmgr_clock_enable() argument 542 cycv_clkmgr_clock_disable(void *priv, struct clk *clk) in cycv_clkmgr_clock_disable() argument [all …]
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/netbsd/sys/arch/arm/rockchip/ |
H A D | rk_cru.c | 124 if (clk == NULL) in rk_cru_clock_get() 131 rk_cru_clock_put(void *priv, struct clk *clk) in rk_cru_clock_put() argument 143 return clk->get_rate(sc, clk); in rk_cru_clock_get_rate() 173 return clk->set_rate(sc, clk, rate); in rk_cru_clock_set_rate() 196 return clk->round_rate(sc, clk, rate); in rk_cru_clock_round_rate() 216 if (clk->enable) in rk_cru_clock_enable() 217 error = clk->enable(sc, clk, 1); in rk_cru_clock_enable() 230 error = clk->enable(sc, clk, 0); in rk_cru_clock_disable() 244 return clk->set_parent(sc, clk, clkp_parent->name); in rk_cru_clock_set_parent() 258 parent = clk->get_parent(sc, clk); in rk_cru_clock_get_parent() [all …]
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/netbsd/sys/arch/arm/sunxi/ |
H A D | sunxi_ccu.c | 136 if (clk == NULL) in sunxi_ccu_clock_get() 143 sunxi_ccu_clock_put(void *priv, struct clk *clk) in sunxi_ccu_clock_put() argument 155 return clk->get_rate(sc, clk); in sunxi_ccu_clock_get_rate() 183 return clk->set_rate(sc, clk, rate); in sunxi_ccu_clock_set_rate() 205 return clk->round_rate(sc, clk, rate); in sunxi_ccu_clock_round_rate() 225 if (clk->enable) in sunxi_ccu_clock_enable() 226 error = clk->enable(sc, clk, 1); in sunxi_ccu_clock_enable() 238 if (clk->enable) in sunxi_ccu_clock_disable() 239 error = clk->enable(sc, clk, 0); in sunxi_ccu_clock_disable() 254 return clk->set_parent(sc, clk, clkp_parent->name); in sunxi_ccu_clock_set_parent() [all …]
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/netbsd/sys/arch/arm/ti/ |
H A D | ti_prcm.c | 53 if (clk == NULL) in ti_prcm_clock_get() 60 ti_prcm_clock_put(void *priv, struct clk *clk) in ti_prcm_clock_put() argument 72 return clk->get_rate(sc, clk); in ti_prcm_clock_get_rate() 100 return clk->set_rate(sc, clk, rate); in ti_prcm_clock_set_rate() 120 if (clk->enable) in ti_prcm_clock_enable() 121 error = clk->enable(sc, clk, 1); in ti_prcm_clock_enable() 134 error = clk->enable(sc, clk, 0); in ti_prcm_clock_disable() 149 return clk->set_parent(sc, clk, clkp_parent->name); in ti_prcm_clock_set_parent() 163 parent = clk->get_parent(sc, clk); in ti_prcm_clock_get_parent() 226 struct clk * [all …]
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/netbsd/sys/arch/arm/amlogic/ |
H A D | meson_clk.c | 137 if (clk == NULL) in meson_clk_clock_get() 144 meson_clk_clock_put(void *priv, struct clk *clk) in meson_clk_clock_put() argument 156 return clk->get_rate(sc, clk); in meson_clk_clock_get_rate() 184 return clk->set_rate(sc, clk, rate); in meson_clk_clock_set_rate() 206 return clk->round_rate(sc, clk, rate); in meson_clk_clock_round_rate() 226 if (clk->enable) in meson_clk_clock_enable() 227 error = clk->enable(sc, clk, 1); in meson_clk_clock_enable() 239 if (clk->enable) in meson_clk_clock_disable() 240 error = clk->enable(sc, clk, 0); in meson_clk_clock_disable() 255 return clk->set_parent(sc, clk, clkp_parent->name); in meson_clk_clock_set_parent() [all …]
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/netbsd/sys/arch/arm/broadcom/ |
H A D | bcm53xx_board.c | 289 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 in bcm53xx_genpll_clock_init() 290 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 in bcm53xx_genpll_clock_init() 291 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 in bcm53xx_genpll_clock_init() 318 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 in bcm53xx_lcpll_clock_init() 320 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 in bcm53xx_lcpll_clock_init() 364 clk->clk_sys = 8*clk->clk_ref; in bcm53xx_clock_init() 395 clk->clk_cpu = clk->clk_ref; in bcm53xx_get_cpu_freq() 396 clk->clk_apb = clk->clk_cpu; in bcm53xx_get_cpu_freq() 401 clk->clk_cpu = clk->clk_sys; in bcm53xx_get_cpu_freq() 402 clk->clk_apb = clk->clk_cpu / 4; in bcm53xx_get_cpu_freq() [all …]
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/netbsd/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
H A D | imx8mq.dtsi | 103 clocks = <&clk IMX8MQ_CLK_ARM>; 311 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 325 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 339 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 353 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 621 <&clk IMX8MQ_CLK_NOC>, 938 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 952 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1262 <&clk IMX8MQ_CLK_AHB>; 1376 <&clk IMX8MQ_CLK_32K>; [all …]
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H A D | imx8mp.dtsi | 52 clocks = <&clk IMX8MP_CLK_ARM>; 63 clocks = <&clk IMX8MP_CLK_ARM>; 74 clocks = <&clk IMX8MP_CLK_ARM>; 85 clocks = <&clk IMX8MP_CLK_ARM>; 416 <&clk IMX8MP_CLK_NOC>, 417 <&clk IMX8MP_CLK_NOC_IO>, 418 <&clk IMX8MP_CLK_GIC>, 421 <&clk IMX8MP_AUDIO_PLL1>, 422 <&clk IMX8MP_AUDIO_PLL2>; 801 <&clk IMX8MP_CLK_AHB>; [all …]
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H A D | imx8mm.dtsi | 64 clocks = <&clk IMX8MM_CLK_ARM>; 290 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 304 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 318 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 332 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 346 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 364 <&clk IMX8MM_CLK_EXT3>; 587 <&clk IMX8MM_CLK_NOC>, 590 <&clk IMX8MM_SYS_PLL3>, 917 <&clk IMX8MM_CLK_AHB>; [all …]
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H A D | imx8mn.dtsi | 64 clocks = <&clk IMX8MN_CLK_ARM>; 270 <&clk IMX8MN_CLK_DUMMY>, 272 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 286 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 300 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 316 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 334 <&clk IMX8MN_CLK_EXT3>; 373 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 591 <&clk IMX8MN_CLK_NOC>, 918 <&clk IMX8MN_CLK_AHB>; [all …]
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/netbsd/sys/arch/hp300/hp300/ |
H A D | clock.c | 124 clk->clk_cr2 = CLK_CR1; in hp300_calibrate_delay() 136 clk->clk_cr2 = CLK_CR1; in hp300_calibrate_delay() 142 csr = clk->clk_sr; in hp300_calibrate_delay() 157 csr = clk->clk_sr; in hp300_calibrate_delay() 168 clk->clk_cr2 = CLK_CR1; in hp300_calibrate_delay() 169 clk->clk_cr1 = CLK_RESET; in hp300_calibrate_delay() 246 clk->clk_cr2 = CLK_CR1; in cpu_initclocks() 247 clk->clk_cr1 = CLK_RESET; in cpu_initclocks() 251 clk->clk_cr2 = CLK_CR1; in cpu_initclocks() 252 clk->clk_cr1 = CLK_IENAB; in cpu_initclocks() [all …]
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/netbsd/sys/dev/fdt/ |
H A D | fdt_clock.c | 84 static struct clk * 88 struct clk *clk = NULL; in fdtbus_clock_get_index_prop() local 114 return clk; in fdtbus_clock_get_index_prop() 117 struct clk * 158 struct clk * 167 struct clk *clk; in fdtbus_clock_enable() local 170 if (clk == NULL) in fdtbus_clock_enable() 179 struct clk *clk; in fdtbus_clock_enable_index() local 182 if (clk == NULL) in fdtbus_clock_enable_index() 194 struct clk * [all …]
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/netbsd/sys/arch/arm/xilinx/ |
H A D | zynq7000_clkc.c | 139 struct clk sc_clk[num_clkid]; 148 static struct clk * 164 zynq7000_clkc_clk_put(void *priv, struct clk *clk) in zynq7000_clkc_clk_put() argument 208 zynq7000_clkc_clk_get_rate(void *priv, struct clk *clk) in zynq7000_clkc_clk_get_rate() argument 214 if (clk == &sc->sc_clk[clkid_armpll]) { in zynq7000_clkc_clk_get_rate() 246 clk == &sc->sc_clk[clkid_sdio1]) { in zynq7000_clkc_clk_get_rate() 249 clk == &sc->sc_clk[clkid_uart1]) { in zynq7000_clkc_clk_get_rate() 266 zynq7000_clkc_clk_enable(void *priv, struct clk *clk) in zynq7000_clkc_clk_enable() argument 272 if (clk == &sc->sc_clk[clkid_cpu_1x]) { in zynq7000_clkc_clk_enable() 330 zynq7000_clkc_clk_disable(void *priv, struct clk *clk) in zynq7000_clkc_clk_disable() argument [all …]
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