Searched refs:cp_int_cntl (Results 1 – 8 of 8) sorted by relevance
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_gfx_v6_0.c | 3243 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local 3247 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state() 3249 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state() 3254 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state() 3265 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local 3306 u32 cp_int_cntl; in gfx_v6_0_set_priv_reg_fault_state() local 3312 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state() 3317 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state() 3331 u32 cp_int_cntl; in gfx_v6_0_set_priv_inst_fault_state() local 3337 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_inst_fault_state() [all …]
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H A D | amdgpu_gfx_v7_0.c | 4714 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local 4718 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state() 4720 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state() 4723 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state() 4725 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state() 4788 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local 4794 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state() 4799 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state() 4813 u32 cp_int_cntl; in gfx_v7_0_set_priv_inst_fault_state() local 4819 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_inst_fault_state() [all …]
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H A D | amdgpu_gfx_v10_0.c | 4815 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local 4836 cp_int_cntl = RREG32(cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state() 4837 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state() 4839 WREG32(cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state() 4842 cp_int_cntl = RREG32(cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state() 4843 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state() 4845 WREG32(cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_evergreen.c | 222 int ring, u32 cp_int_cntl); 4501 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local 4532 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set() 4545 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set() 4546 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set() 4569 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set() 4573 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
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H A D | radeon_ni.c | 1400 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument 1403 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
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H A D | radeon_r600.c | 3799 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local 3857 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set() 3858 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set() 3909 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
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H A D | radeon_si.c | 6060 u32 cp_int_cntl; in si_irq_set() local 6078 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set() 6090 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set() 6110 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
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H A D | radeon_cik.c | 7045 u32 cp_int_cntl; in cik_irq_set() local 7065 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set() 7067 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set() 7091 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set() 7245 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
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