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Searched refs:dpm_table (Results 1 – 19 of 19) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega12_hwmgr.c567 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
580 dpm_table = &(data->dpm_table.gfx_table); in vega12_setup_default_dpm_tables()
593 dpm_table = &(data->dpm_table.mem_table); in vega12_setup_default_dpm_tables()
606 dpm_table = &(data->dpm_table.eclk_table); in vega12_setup_default_dpm_tables()
619 dpm_table = &(data->dpm_table.vclk_table); in vega12_setup_default_dpm_tables()
632 dpm_table = &(data->dpm_table.dclk_table); in vega12_setup_default_dpm_tables()
645 dpm_table = &(data->dpm_table.dcef_table); in vega12_setup_default_dpm_tables()
680 dpm_table = &(data->dpm_table.phy_table); in vega12_setup_default_dpm_tables()
1726 dpm_table = &(data->dpm_table.gfx_table); in vega12_get_sclks()
1758 dpm_table = &(data->dpm_table.mem_table); in vega12_get_memclocks()
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H A Damdgpu_vega20_hwmgr.c601 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
622 dpm_table = &(data->dpm_table.mem_table); in vega20_setup_memclk_dpm_table()
654 dpm_table = &(data->dpm_table.soc_table); in vega20_setup_default_dpm_tables()
667 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_default_dpm_tables()
674 dpm_table = &(data->dpm_table.mem_table); in vega20_setup_default_dpm_tables()
681 dpm_table = &(data->dpm_table.eclk_table); in vega20_setup_default_dpm_tables()
694 dpm_table = &(data->dpm_table.vclk_table); in vega20_setup_default_dpm_tables()
707 dpm_table = &(data->dpm_table.dclk_table); in vega20_setup_default_dpm_tables()
720 dpm_table = &(data->dpm_table.dcef_table); in vega20_setup_default_dpm_tables()
755 dpm_table = &(data->dpm_table.phy_table); in vega20_setup_default_dpm_tables()
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H A Damdgpu_vega10_hwmgr.c1348 dpm_table = &(data->dpm_table.soc_table); in vega10_setup_default_dpm_tables()
1355 dpm_table = &(data->dpm_table.gfx_table); in vega10_setup_default_dpm_tables()
1366 dpm_table = &(data->dpm_table.mem_table); in vega10_setup_default_dpm_tables()
1376 dpm_table = &(data->dpm_table.eclk_table); in vega10_setup_default_dpm_tables()
1392 dpm_table = &(data->dpm_table.vclk_table); in vega10_setup_default_dpm_tables()
1406 dpm_table = &(data->dpm_table.dclk_table); in vega10_setup_default_dpm_tables()
1421 dpm_table = &(data->dpm_table.dcef_table); in vega10_setup_default_dpm_tables()
1442 dpm_table = &(data->dpm_table.phy_table); in vega10_setup_default_dpm_tables()
1704 dpm_table = &(data->dpm_table.soc_table); in vega10_populate_all_graphic_levels()
5193 dpm_table = &data->dpm_table.soc_table; in vega10_odn_update_soc_table()
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H A Damdgpu_smu7_hwmgr.c638 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); in smu7_reset_dpm_tables()
641 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
646 &data->dpm_table.mclk_table, in smu7_reset_dpm_tables()
704 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
718 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
798 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
801 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
814 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
816 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
3658 struct smu7_dpm_table *dpm_table = &data->dpm_table; in smu7_get_maximum_link_speed() local
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H A Damdgpu_smu_helper.c355 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
357 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
359 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
360 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
371 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
372 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
373 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
382 for (i = dpm_table->count; i > 0; i--) { in phm_get_dpm_level_enable_mask_value()
384 if (dpm_table->dpm_level[i - 1].enabled) in phm_get_dpm_level_enable_mask_value()
454 for (i = 0; i < dpm_table->count; i++) { in phm_find_boot_level()
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H A Dsmu7_hwmgr.h206 struct smu7_dpm_table dpm_table; member
H A Dvega10_hwmgr.h313 struct vega10_dpm_table dpm_table; member
H A Dvega12_hwmgr.h316 struct vega12_dpm_table dpm_table; member
H A Dvega20_hwmgr.h439 struct vega20_dpm_table dpm_table; member
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_vega20_ppt.c2106 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2108 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2128 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2130 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2170 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2172 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2187 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2189 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2204 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
2206 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; in vega20_apply_clocks_adjust_rules()
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H A Damdgpu_arcturus_ppt.c429 dpm_table = smu_dpm->dpm_context; in arcturus_set_default_dpm_table()
576 dpm_table = smu_dpm->dpm_context; in arcturus_populate_umd_state_clk()
577 gfx_table = &(dpm_table->gfx_table); in arcturus_populate_umd_state_clk()
578 mem_table = &(dpm_table->mem_table); in arcturus_populate_umd_state_clk()
602 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; in arcturus_get_clk_table()
634 dpm_table = smu_dpm->dpm_context; in arcturus_print_clk_levels()
745 struct arcturus_dpm_table *dpm_table = in arcturus_upload_dpm_level() local
801 struct arcturus_dpm_table *dpm_table; in arcturus_force_clk_levels() local
809 dpm_table = smu->smu_dpm.dpm_context; in arcturus_force_clk_levels()
1163 struct arcturus_dpm_table *dpm_table = in arcturus_force_dpm_limit_value() local
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_fiji_smumgr.c519 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
560 dpm_table->Liquid_I2C_LineSCL = uc_scl; in fiji_populate_bapm_parameters_in_dpm_table()
561 dpm_table->Liquid_I2C_LineSDA = uc_sda; in fiji_populate_bapm_parameters_in_dpm_table()
564 dpm_table->Vr_I2C_LineSCL = uc_scl; in fiji_populate_bapm_parameters_in_dpm_table()
565 dpm_table->Vr_I2C_LineSDA = uc_sda; in fiji_populate_bapm_parameters_in_dpm_table()
568 dpm_table->Plx_I2C_LineSCL = uc_scl; in fiji_populate_bapm_parameters_in_dpm_table()
569 dpm_table->Plx_I2C_LineSDA = uc_sda; in fiji_populate_bapm_parameters_in_dpm_table()
837 struct smu7_dpm_table *dpm_table = &data->dpm_table; in fiji_populate_smc_link_level() local
1011 struct smu7_dpm_table *dpm_table = &data->dpm_table; in fiji_populate_all_graphic_levels() local
1049 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
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H A Damdgpu_iceland_smumgr.c772 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
793 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
968 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
987 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
1001 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
1006 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1355 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_memory_levels() local
1875 dpm_table->DTETjOffset = 0; in iceland_populate_bapm_parameters_in_dpm_table()
1878 dpm_table->GpuTjHyst = 8; in iceland_populate_bapm_parameters_in_dpm_table()
1887 dpm_table->PPM_PkgPwrLimit = 0; in iceland_populate_bapm_parameters_in_dpm_table()
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H A Damdgpu_ci_smumgr.c479 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
491 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
497 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
732 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
734 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
742 dpm_table->PPM_PkgPwrLimit = 0; in ci_populate_bapm_parameters_in_dpm_table()
743 dpm_table->PPM_TemperatureLimit = 0; in ci_populate_bapm_parameters_in_dpm_table()
1003 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_smc_link_level() local
1019 (uint8_t)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
1307 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_memory_levels() local
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H A Damdgpu_vegam_smumgr.c578 struct smu7_dpm_table *dpm_table = &data->dpm_table; in vegam_populate_smc_link_level() local
595 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
870 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_graphic_levels() local
893 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
911 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
915 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1040 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_memory_levels() local
1056 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1069 (uint8_t)dpm_table->mclk_table.count; in vegam_populate_all_memory_levels()
1073 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
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H A Damdgpu_tonga_smumgr.c515 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
696 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
731 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
736 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
1096 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_memory_levels() local
1845 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in tonga_populate_bapm_parameters_in_dpm_table()
1853 dpm_table->GpuTjHyst = 8; in tonga_populate_bapm_parameters_in_dpm_table()
1857 dpm_table->BAPM_TEMP_GRADIENT = in tonga_populate_bapm_parameters_in_dpm_table()
1865 dpm_table->BAPMTI_R[i][j][k] = in tonga_populate_bapm_parameters_in_dpm_table()
1867 dpm_table->BAPMTI_RC[i][j][k] = in tonga_populate_bapm_parameters_in_dpm_table()
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H A Damdgpu_polaris10_smumgr.c776 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
793 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
986 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
1009 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1024 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1034 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1059 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1133 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_memory_levels() local
1149 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1151 if (i == dpm_table->mclk_table.count - 1) { in polaris10_populate_all_memory_levels()
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ci_dpm.c451 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
453 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
2636 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level() local
3285 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels() local
3332 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels() local
3490 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3492 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3503 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3910 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3917 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
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H A Dci_dpm.h197 struct ci_dpm_table dpm_table; member