| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 615 return isAdd; in EncodeAddrModeOpValues()
1021 if (isAdd) in getAddrModeImm12OpValue()
1052 if (isAdd) in getT2ScaledImmOpValue()
1100 if (isAdd) in getMveAddrModeQOpValue()
1143 if (isAdd) in getT2AddrModeImm8s4OpValue()
1170 if (isAdd) in getT2AddrModeImm7s4OpValue()
1276 if (isAdd) in getLdStSORegOpValue()
1423 bool isAdd; in getAddrMode5OpValue() local
1448 if (isAdd) in getAddrMode5OpValue()
1463 bool isAdd; in getAddrMode5FP16OpValue() local
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| H A D | ARMAsmBackend.cpp | 498 bool isAdd = true; in adjustFixupValue() local
501 isAdd = false; in adjustFixupValue()
507 Value |= isAdd << 23; in adjustFixupValue()
727 bool isAdd = true; in adjustFixupValue() local
730 isAdd = false; in adjustFixupValue()
747 bool isAdd = true; in adjustFixupValue() local
750 isAdd = false; in adjustFixupValue()
758 Value |= isAdd << 23; in adjustFixupValue()
774 bool isAdd = true; in adjustFixupValue() local
777 isAdd = false; in adjustFixupValue()
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| /netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 111 FLAG(isAdd) in EmitInstrDocs()
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| H A D | CodeGenInstruction.h | 248 bool isAdd : 1; variable
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| H A D | CodeGenInstruction.cpp | 382 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
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| H A D | InstrInfoEmitter.cpp | 954 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; in emitRecord()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 270 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 861 bool isAdd; member
3274 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3276 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
3285 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3288 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
3295 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3825 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
5626 bool isAdd = true; in parsePostIdxReg() local
5632 isAdd = false; in parsePostIdxReg()
5708 bool isAdd = true; in parseAM3Offset() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 2990 // {12} isAdd
3009 // {12} isAdd
3026 // {12} isAdd
3045 // {12} isAdd
3324 // {12} isAdd
3343 // {12} isAdd
3365 // {12} isAdd
3384 // {12} isAdd
3813 let isAdd = 1 in
3829 let isAdd = 1 in
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| H A D | ARMInstrFormats.td | 797 // {12} isAdd
815 // {12} isAdd
836 // {12} isAdd
889 // {8} isAdd
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| H A D | ARMInstrThumb.td | 966 let isAdd = 1 in {
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| H A D | ARMInstrThumb2.td | 2341 let isAdd = 1 in
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 442 if (DI->getDesc().isAdd()) { in findInductionRegister()
1639 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
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| H A D | HexagonDepInstrInfo.td | 220 let isAdd = 1;
236 let isAdd = 1;
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | Target.td | 529 bit isAdd = false; // Is this instruction an add instruction?
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| /netbsd/external/apache2/llvm/dist/llvm/docs/TableGen/ |
| H A D | ProgRef.rst | 1907 bit isAdd = 0;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 42925 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
42930 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
42935 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
42940 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
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