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Searched refs:isTypeDesirableForOp (Results 1 – 7 of 7) sorted by relevance

/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h310 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
H A DSIISelLowering.cpp1583 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const { in isTypeDesirableForOp() function in SITargetLowering
1606 return TargetLowering::isTypeDesirableForOp(Op, VT); in isTypeDesirableForOp()
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h962 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
H A DX86ISelLowering.cpp50968 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { in isTypeDesirableForOp() function in X86TargetLowering
/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1289 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntBinOp()
1357 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntShiftOp()
1406 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteExtend()
1437 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteLoad()
4821 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5161 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
5162 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
8088 TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) { in distributeTruncateThroughAnd()
8823 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
12090 TLI.isTypeDesirableForOp(ISD::SHL, VT)) { in visitTRUNCATE()
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H A DTargetLowering.cpp1482 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
2026 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
3598 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3582 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { in isTypeDesirableForOp() function