/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
H A D | amdgpu_dc_link_dp.c | 278 for (lane = 0; lane < in dpcd_set_lt_pattern_and_lane_settings() 356 for (lane = 0; lane < (uint32_t)(ln_count); lane++) { in is_cr_done() 373 for (lane = 0; lane < (uint32_t)(ln_count); lane++) { in is_ch_eq_done() 513 for (lane = 0; lane < in find_max_drive_settings() 558 for (lane = 0; lane < in get_lane_status_and_drive_settings() 615 for (lane = 0; lane < in get_lane_status_and_drive_settings() 657 for (lane = 0; lane < in dpcd_set_lane_settings() 729 for (lane = 0; lane < in is_max_vs_reached() 1156 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in initialize_training_settings() 2583 for (lane = 0; lane < in dp_test_send_phy_test_pattern() [all …]
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/netbsd/sys/external/bsd/drm2/dist/drm/i915/display/ |
H A D | intel_dp_link_training.c | 48 int lane; in intel_get_adjust_train() local 52 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train() 53 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); in intel_get_adjust_train() 54 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in intel_get_adjust_train() 70 for (lane = 0; lane < 4; lane++) in intel_get_adjust_train() 71 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train() 124 int lane; in intel_dp_link_max_vswing_reached() local 126 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached() 127 if ((intel_dp->train_set[lane] & in intel_dp_link_max_vswing_reached()
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H A D | intel_dpio_phy.c | 602 int lane; in bxt_ddi_phy_set_lane_optim_mask() local 606 for (lane = 0; lane < 4; lane++) { in bxt_ddi_phy_set_lane_optim_mask() 607 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_set_lane_optim_mask() 614 if (lane_lat_optim_mask & BIT(lane)) in bxt_ddi_phy_set_lane_optim_mask() 617 I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); in bxt_ddi_phy_set_lane_optim_mask() 628 int lane; in bxt_ddi_phy_get_lane_lat_optim_mask() local 634 for (lane = 0; lane < 4; lane++) { in bxt_ddi_phy_get_lane_lat_optim_mask() 635 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_get_lane_lat_optim_mask() 638 mask |= BIT(lane); in bxt_ddi_phy_get_lane_lat_optim_mask()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMInstrNEON.td | 1163 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", 1198 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", 1236 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", 1272 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", 1314 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", 2246 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm", 2281 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>, 2318 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm", 2352 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", 2392 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm", [all …]
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/netbsd/sys/external/bsd/drm2/dist/drm/ |
H A D | drm_dp_helper.c | 62 int lane) in dp_get_lane_status() argument 65 int s = (lane & 1) * 4; in dp_get_lane_status() 75 int lane; in drm_dp_channel_eq_ok() local 81 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok() 93 int lane; in drm_dp_clock_recovery_ok() local 96 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok() 106 int lane) in drm_dp_get_adjust_request_voltage() argument 109 int s = ((lane & 1) ? in drm_dp_get_adjust_request_voltage() 119 int lane) in drm_dp_get_adjust_request_pre_emphasis() argument 122 int s = ((lane & 1) ? in drm_dp_get_adjust_request_pre_emphasis() [all …]
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/netbsd/sys/arch/arm/rockchip/ |
H A D | rk3399_pcie_phy.c | 120 uint8_t * const lane = priv; in rkpciephy_phy_enable() local 125 rkpcie_phy_poweron(sc, *lane); in rkpciephy_phy_enable() 126 sc->sc_phys_on |= 1U << *lane; in rkpciephy_phy_enable() 129 sc->sc_phys_on &= ~(1U << *lane); in rkpciephy_phy_enable() 202 rkpcie_phy_poweron(struct rkpciephy_softc *sc, u_int lane) in rkpcie_phy_poweron() argument 219 RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0); in rkpcie_phy_poweron()
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/netbsd/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
H A D | nouveau_nvkm_engine_disp_dp.c | 95 u8 lpre = (lane & 0x0c) >> 2; in nvkm_dp_train_drive() 96 u8 lvsw = (lane & 0x03) >> 0; in nvkm_dp_train_drive() 181 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) in nvkm_dp_train_eq() 183 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || in nvkm_dp_train_eq() 184 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) in nvkm_dp_train_eq() 209 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { in nvkm_dp_train_cr() 494 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; in nvkm_dp_acquire() local 495 if (!(lane & DPCD_LS02_LANE0_CR_DONE) || in nvkm_dp_acquire() 496 !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || in nvkm_dp_acquire() 497 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) { in nvkm_dp_acquire() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/docs/ |
H A D | BigEndianNEON.rst | 22 This trivial C function takes a vector of four ints and sets the zero'th lane to the value "42":: 61 …use of the byte swapping the lane indices end up being swapped! The zero'th item as laid out in me… 95 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, b… 97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``. 98 …hat rely on lane layout, and for every access to an individual lane (``insertelement``/``extractel… 109 …re not - the lane size is encoded within them. This is important across an ABI boundary, because i… 128 So to preserve ABI compatibility, we need to use the ``LDR`` lane layout across function calls. 133 …128-bit aligned, whereas ``LD1`` only requires it to be as aligned as the lane size. If we canonic… 152 …issue with lane ordering, it was decided, would have to change target-agnostic compiler passes and… 159 …e vector loads and stores. The exception is one-lane vectors [1]_ - these by definition cannot hav… [all …]
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/netbsd/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
H A D | armada-xp-mv78460.dtsi | 129 marvell,pcie-lane = <0>; 147 marvell,pcie-lane = <1>; 165 marvell,pcie-lane = <2>; 183 marvell,pcie-lane = <3>; 201 marvell,pcie-lane = <0>; 219 marvell,pcie-lane = <1>; 237 marvell,pcie-lane = <2>; 255 marvell,pcie-lane = <3>; 273 marvell,pcie-lane = <0>; 291 marvell,pcie-lane = <0>;
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H A D | armada-xp-mv78260.dtsi | 108 marvell,pcie-lane = <0>; 126 marvell,pcie-lane = <1>; 144 marvell,pcie-lane = <2>; 162 marvell,pcie-lane = <3>; 180 marvell,pcie-lane = <0>; 198 marvell,pcie-lane = <1>; 216 marvell,pcie-lane = <2>; 234 marvell,pcie-lane = <3>; 252 marvell,pcie-lane = <0>;
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H A D | armada-xp-mv78230.dtsi | 93 marvell,pcie-lane = <0>; 111 marvell,pcie-lane = <1>; 129 marvell,pcie-lane = <2>; 147 marvell,pcie-lane = <3>; 165 marvell,pcie-lane = <0>;
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H A D | armada-385.dtsi | 79 marvell,pcie-lane = <0>; 98 marvell,pcie-lane = <0>; 117 marvell,pcie-lane = <0>; 139 marvell,pcie-lane = <0>;
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H A D | armada-380.dtsi | 74 marvell,pcie-lane = <0>; 93 marvell,pcie-lane = <0>; 112 marvell,pcie-lane = <0>;
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_atombios_dp.c | 217 int lane; in amdgpu_atombios_dp_get_adjust_train() local 219 for (lane = 0; lane < lane_count; lane++) { in amdgpu_atombios_dp_get_adjust_train() 220 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); in amdgpu_atombios_dp_get_adjust_train() 221 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in amdgpu_atombios_dp_get_adjust_train() 224 lane, in amdgpu_atombios_dp_get_adjust_train() 244 for (lane = 0; lane < 4; lane++) in amdgpu_atombios_dp_get_adjust_train() 245 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_atombios_dp.c | 275 int lane; in dp_get_adjust_train() local 277 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train() 278 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); in dp_get_adjust_train() 279 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in dp_get_adjust_train() 282 lane, in dp_get_adjust_train() 302 for (lane = 0; lane < 4; lane++) in dp_get_adjust_train() 303 train_set[lane] = v | p; in dp_get_adjust_train()
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/netbsd/external/gpl3/gcc/dist/gcc/config/arm/ |
H A D | neon.md | 1747 half, lane)); 1791 rtx lane 1796 half, lane)); 3331 int lane; 3347 gcc_assert ((lane ==0) || (lane == 1)); 4945 ;; The lane numbers in the RTL are in GCC lane order, having been flipped 4947 ;; lane order here. 4981 if (lane >= max / 2) 4983 lane -= max / 2; 6363 if (lane < half) [all …]
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/netbsd/external/gpl3/gcc/dist/gcc/ |
H A D | tree-vect-slp.cc | 1882 for (unsigned lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() local 1903 for (lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() 1942 for (lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() 1972 for (lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() 1989 for (lane = 1; lane < group_size; ++lane) in vect_build_slp_tree_2() 2027 for (unsigned lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() local 2034 for (lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() 2044 for (lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() 2062 for (lane = 0; lane < group_size; ++lane) in vect_build_slp_tree_2() 2068 for (lane = 1; lane < group_size; ++lane) in vect_build_slp_tree_2() [all …]
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/netbsd/sys/arch/arm/nvidia/ |
H A D | tegra210_xusbpad.c | 663 tegra210_xusbpad_find_func(const struct tegra210_xusbpad_lane *lane, in tegra210_xusbpad_find_func() argument 666 for (int n = 0; n < lane->nfuncs; n++) in tegra210_xusbpad_find_func() 667 if (strcmp(lane->funcs[n], func) == 0) in tegra210_xusbpad_find_func() 685 const struct tegra210_xusbpad_lane *lane; in tegra210_xusbpad_configure_lane() local 700 lane = tegra210_xusbpad_find_lane(name); in tegra210_xusbpad_configure_lane() 701 if (lane == NULL) { in tegra210_xusbpad_configure_lane() 705 func = tegra210_xusbpad_find_func(lane, function); in tegra210_xusbpad_configure_lane() 712 SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask); in tegra210_xusbpad_configure_lane() 714 if (lane->enable) in tegra210_xusbpad_configure_lane() 715 lane->enable(sc, lane->index); in tegra210_xusbpad_configure_lane()
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/netbsd/external/apache2/argon2/dist/phc-winner-argon2/src/ |
H A D | ref.c | 114 input_block.v[1] = position.lane; in fill_segment() 133 curr_offset = position.lane * instance->lane_length + in fill_segment() 167 ref_lane = position.lane; in fill_segment() 175 ref_lane == position.lane); in fill_segment()
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/netbsd/external/gpl3/gcc.old/dist/gcc/config/arm/ |
H A D | neon.md | 2138 half, lane)); 2182 rtx lane 2187 half, lane)); 3658 int lane; 3674 gcc_assert ((lane ==0) || (lane == 1)); 5272 ;; The lane numbers in the RTL are in GCC lane order, having been flipped 5274 ;; lane order here. 5308 if (lane >= max / 2) 5310 lane -= max / 2; 6724 if (lane < half) [all …]
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/netbsd/sys/external/isc/libsodium/dist/src/libsodium/crypto_pwhash/argon2/ |
H A D | argon2-fill-block-ssse3.c | 111 input_block.v[1] = position->lane; in generate_addresses() 178 curr_offset = position.lane * instance->lane_length + in fill_segment_ssse3() 215 ref_lane = position.lane; in fill_segment_ssse3() 223 ref_lane == position.lane); in fill_segment_ssse3()
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H A D | argon2-fill-block-avx2.c | 112 input_block.v[1] = position->lane; in generate_addresses() 179 curr_offset = position.lane * instance->lane_length + in fill_segment_avx2() 216 ref_lane = position.lane; in fill_segment_avx2() 224 ref_lane == position.lane); in fill_segment_avx2()
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H A D | argon2-fill-block-avx512f.c | 117 input_block.v[1] = position->lane; in generate_addresses() 184 curr_offset = position.lane * instance->lane_length + in fill_segment_avx512f() 221 ref_lane = position.lane; in fill_segment_avx512f() 229 ref_lane == position.lane); in fill_segment_avx512f()
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H A D | argon2-fill-block-ref.c | 123 input_block.v[1] = position->lane; in generate_addresses() 177 curr_offset = position.lane * instance->lane_length + in fill_segment_ref() 211 ref_lane = position.lane; in fill_segment_ref() 219 ref_lane == position.lane); in fill_segment_ref()
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/netbsd/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/ |
H A D | r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 19 * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode. 21 * imx219 as the imx219 endpoint driver supports only 2 lane mode.
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