/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
H A D | amdgpu_dcn10_dpp_cm.c | 124 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap() 126 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap() 219 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix() 221 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix() 275 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field() 279 reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; in dpp1_cm_get_reg_field() 283 reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_reg_field() 302 reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field() 310 reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_degamma_reg_field() 475 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp1_program_input_csc() [all …]
|
H A D | dcn10_cm_common.h | 73 struct xfer_func_mask masks; member 88 struct cm_color_matrix_mask masks; member
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
H A D | amdgpu_dce_i2c_hw.c | 91 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status() 604 const struct dce_i2c_mask *masks) in dce_i2c_hw_construct() argument 611 dce_i2c_hw->masks = masks; in dce_i2c_hw_construct() 627 const struct dce_i2c_mask *masks) in dce100_i2c_hw_construct() argument 634 masks); in dce100_i2c_hw_construct() 644 const struct dce_i2c_mask *masks) in dce112_i2c_hw_construct() argument 651 masks); in dce112_i2c_hw_construct() 661 const struct dce_i2c_mask *masks) in dcn1_i2c_hw_construct() argument 668 masks); in dcn1_i2c_hw_construct() 678 const struct dce_i2c_mask *masks) in dcn2_i2c_hw_construct() argument [all …]
|
H A D | dce_i2c_hw.h | 275 const struct dce_i2c_mask *masks; member 284 const struct dce_i2c_mask *masks); 292 const struct dce_i2c_mask *masks); 300 const struct dce_i2c_mask *masks); 308 const struct dce_i2c_mask *masks); 316 const struct dce_i2c_mask *masks);
|
H A D | amdgpu_dce_hwseq.c | 43 hws->shifts->field_name, hws->masks->field_name 80 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock() 125 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
|
H A D | dce_audio.h | 130 const struct dce_audio_mask *masks; member 138 const struct dce_audio_mask *masks);
|
/netbsd/external/cddl/osnet/dist/common/acl/ |
H A D | acl_common.c | 1585 masks->deny1 = 0; in acl_trivial_access_masks() 1587 masks->deny1 |= read_mask; in acl_trivial_access_masks() 1593 masks->deny2 = 0; in acl_trivial_access_masks() 1601 masks->allow0 = 0; in acl_trivial_access_masks() 1643 trivial_acl_t masks; in acl_trivial_create() local 1648 if (masks.allow0) in acl_trivial_create() 1650 if (masks.deny1) in acl_trivial_create() 1652 if (masks.deny2) in acl_trivial_create() 1658 if (masks.allow0) { in acl_trivial_create() 1662 if (masks.deny1) { in acl_trivial_create() [all …]
|
/netbsd/external/bsd/openldap/dist/libraries/liblunicode/ucdata/ |
H A D | ucdata.c | 1317 if (masks & UCDATA_CTYPE) in ucdata_load() 1319 if (masks & UCDATA_CASE) in ucdata_load() 1325 if (masks & UCDATA_NUM) in ucdata_load() 1327 if (masks & UCDATA_COMP) in ucdata_load() 1336 ucdata_unload(int masks) in ucdata_unload() argument 1340 if (masks & UCDATA_CASE) in ucdata_unload() 1346 if (masks & UCDATA_NUM) in ucdata_unload() 1348 if (masks & UCDATA_COMP) in ucdata_unload() 1364 if (masks & UCDATA_CASE) in ucdata_reload() 1370 if (masks & UCDATA_NUM) in ucdata_reload() [all …]
|
H A D | api.txt | 38 void ucdata_load(char *paths, int masks) 42 files to be loaded are specified in the `masks' parameter as a bitwise 52 void ucdata_unload(int masks) 54 This function unloads the data tables specified in the `masks' parameter. 64 void ucdata_reload(char *paths, int masks) 68 specified in the `masks' parameter as a bitwise combination of the macros
|
/netbsd/sys/external/bsd/drm2/dist/drm/via/ |
H A D | via_irq.c | 224 maskarray_t *masks; in via_driver_irq_wait() local 247 masks = dev_priv->irq_masks; in via_driver_irq_wait() 252 if (masks[real_irq][2] && !force_sequence) { in via_driver_irq_wait() 255 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == in via_driver_irq_wait() 256 masks[irq][4])); in via_driver_irq_wait() 266 if (masks[real_irq][2] && !force_sequence) { in via_driver_irq_wait() 268 ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) == in via_driver_irq_wait() 269 masks[irq][4])); in via_driver_irq_wait()
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
H A D | amdgpu_dcn20_mpc.c | 171 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc() 173 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc() 229 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default() 231 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default() 257 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field() 259 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field() 261 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field() 265 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field() 267 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field() 269 reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc2_ogam_get_reg_field() [all …]
|
H A D | amdgpu_dcn20_dpp_cm.c | 195 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap() 197 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap() 290 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc() 292 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc() 368 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() 370 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field() 372 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field() 377 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field() 379 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field() 381 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field() [all …]
|
/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrGISel.td | 29 // G_SHUFFLE_VECTORs with appropriate masks. 37 // G_SHUFFLE_VECTORs with appropriate masks. 45 // G_SHUFFLE_VECTORs with appropriate masks. 53 // G_SHUFFLE_VECTORs with appropriate masks. 61 // G_SHUFFLE_VECTORs with appropriate masks. 69 // G_SHUFFLE_VECTORs with appropriate masks. 77 // G_SHUFFLE_VECTORs with appropriate masks. 85 // G_SHUFFLE_VECTORs with appropriate masks. 115 // G_SHUFFLE_VECTORs with appropriate masks. 123 // G_SHUFFLE_VECTORs with appropriate masks. [all …]
|
/netbsd/external/bsd/pdisk/dist/ |
H A D | bitfield.c | 47 const uint32_t masks[] = { variable 84 m = masks[length]; in bitfield_set() 100 m = masks[length]; in bitfield_get()
|
/netbsd/external/bsd/openldap/dist/libraries/liblunicode/ure/ |
H A D | urestubs.c | 72 } masks[32] = { variable 126 mask1 |= masks[i].mask1; in _ure_matches_properties() 127 mask2 |= masks[i].mask2; in _ure_matches_properties()
|
/netbsd/sys/arch/dreamcast/dreamcast/ |
H A D | sysasic.c | 209 volatile uint32_t *masks, *stats; in sysasic_intr_enable() local 224 masks = (volatile uint32_t *) SYSASIC_INTR_EN(syh->syh_idx); in sysasic_intr_enable() 237 masks[evmap] = syh->syh_events[evmap]; in sysasic_intr_enable() 240 masks[evmap] = syh->syh_events[evmap] & ~evbit; in sysasic_intr_enable()
|
/netbsd/sys/dev/pci/ |
H A D | hifn7751reg.h | 373 volatile u_int16_t masks; member 395 volatile u_int16_t masks; member 425 volatile u_int16_t masks; member 453 volatile u_int16_t masks; member
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/ |
H A D | amdgpu_hw_factory_dcn10.c | 162 generic->masks = &generic_mask[en]; in define_generic_registers() 187 ddc->masks = &ddc_mask; in define_ddc_registers() 197 hpd->masks = &hpd_mask; in define_hpd_registers()
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/ |
H A D | amdgpu_hw_factory_dcn21.c | 170 generic->masks = &generic_mask[en]; in define_generic_registers() 195 ddc->masks = &ddc_mask[en]; in define_ddc_registers() 205 hpd->masks = &hpd_mask; in define_hpd_registers()
|
/netbsd/sys/dev/microcode/aic7xxx/ |
H A D | aicasm_symbol.c | 469 symlist_t masks; in symtable_dump() local 485 SLIST_INIT(&masks); in symtable_dump() 505 symlist_add(&masks, cursym, SYMLIST_SORT); in symtable_dump() 567 while (SLIST_FIRST(&masks) != NULL) { in symtable_dump() 570 curnode = SLIST_FIRST(&masks); in symtable_dump() 571 SLIST_REMOVE_HEAD(&masks, links); in symtable_dump()
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/ |
H A D | amdgpu_hw_factory_dcn20.c | 205 ddc->masks = &ddc_mask[en]; in define_ddc_registers() 215 hpd->masks = &hpd_mask; in define_hpd_registers() 225 generic->masks = &generic_mask[en]; in define_generic_registers()
|
/netbsd/crypto/external/bsd/openssl/dist/doc/man3/ |
H A D | OPENSSL_s390xcap.pod | 42 The name of an instruction followed by two 64-bit masks. The part of the 50 Store-facility-list-extended (stfle) followed by three 64-bit masks. The 56 The 64-bit masks are specified in hexadecimal notation. The 0x prefix is 60 rows separate the individual 64-bit masks. The bit numbers in the first
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/ |
H A D | amdgpu_hw_factory_dce110.c | 142 ddc->masks = &ddc_mask; in define_ddc_registers() 152 hpd->masks = &hpd_mask; in define_hpd_registers()
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/ |
H A D | amdgpu_hw_factory_dce80.c | 142 ddc->masks = &ddc_mask; in define_ddc_registers() 152 hpd->masks = &hpd_mask; in define_hpd_registers()
|
/netbsd/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/ |
H A D | amdgpu_hw_factory_dce120.c | 155 ddc->masks = &ddc_mask; in define_ddc_registers() 165 hpd->masks = &hpd_mask; in define_hpd_registers()
|