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Searched refs:mclk_mask (Results 1 – 12 of 12) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_renoir_ppt.c549 uint32_t *mclk_mask, in renoir_get_profiling_clk_mask() argument
557 if (mclk_mask) in renoir_get_profiling_clk_mask()
558 *mclk_mask = 0; in renoir_get_profiling_clk_mask()
564 if(mclk_mask) in renoir_get_profiling_clk_mask()
565 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; in renoir_get_profiling_clk_mask()
726 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
743 &mclk_mask, in renoir_set_performance_level()
748 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false); in renoir_set_performance_level()
H A Damdgpu_smu_v12_0.c383 uint32_t mclk_mask, soc_mask; in smu_v12_0_get_dpm_ultimate_freq() local
388 &mclk_mask, in smu_v12_0_get_dpm_ultimate_freq()
408 ret = smu_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in smu_v12_0_get_dpm_ultimate_freq()
H A Damdgpu_navi10_ppt.c1420 uint32_t *mclk_mask, in navi10_get_profiling_clk_mask() argument
1430 if (mclk_mask) in navi10_get_profiling_clk_mask()
1431 *mclk_mask = 0; in navi10_get_profiling_clk_mask()
1440 if(mclk_mask) { in navi10_get_profiling_clk_mask()
1444 *mclk_mask = level_count - 1; in navi10_get_profiling_clk_mask()
1768 uint32_t sclk_mask, mclk_mask, soc_mask; in navi10_set_performance_level() local
1787 &mclk_mask, in navi10_set_performance_level()
1792 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false); in navi10_set_performance_level()
H A Dsmu_internal.h142 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \ argument
143 … (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : …
H A Damdgpu_arcturus_ppt.c1245 uint32_t *mclk_mask, in arcturus_get_profiling_clk_mask() argument
1262 *mclk_mask = 0; in arcturus_get_profiling_clk_mask()
1269 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL; in arcturus_get_profiling_clk_mask()
1276 *mclk_mask = 0; in arcturus_get_profiling_clk_mask()
1279 *mclk_mask = mem_dpm_table->count - 1; in arcturus_get_profiling_clk_mask()
H A Damdgpu_smu_v11_0.c1911 uint32_t sclk_mask, mclk_mask, soc_mask; in smu_v11_0_set_performance_level() local
1929 &mclk_mask, in smu_v11_0_set_performance_level()
1934 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false); in smu_v11_0_set_performance_level()
H A Damdgpu_vega20_ppt.c1976 uint32_t *mclk_mask, in vega20_get_profiling_clk_mask() argument
1992 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
1999 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2006 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2009 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega12_hwmgr.c1588 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1596 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1603 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; in vega12_get_profiling_clk_mask()
1610 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1613 *mclk_mask = mem_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1643 uint32_t mclk_mask = 0; in vega12_dpm_force_dpm_level() local
1660 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1664 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega12_dpm_force_dpm_level()
H A Damdgpu_vega20_hwmgr.c2484 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2492 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2499 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2506 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2509 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2683 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2702 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2706 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega20_dpm_force_dpm_level()
H A Damdgpu_smu7_hwmgr.c2734 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
2752 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
2755 *mclk_mask = golden_dpm_table->mclk_table.count - 2; in smu7_get_profiling_clk()
2797 *mclk_mask = 0; in smu7_get_profiling_clk()
2799 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
2813 uint32_t mclk_mask = 0; in smu7_force_dpm_level() local
2817 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2833 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2837 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
H A Damdgpu_vega10_hwmgr.c4086 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4096 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; in vega10_get_profiling_clk_mask()
4104 *mclk_mask = 0; in vega10_get_profiling_clk_mask()
4114 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; in vega10_get_profiling_clk_mask()
4206 uint32_t mclk_mask = 0; in vega10_dpm_force_dpm_level() local
4210 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4226 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4230 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in vega10_dpm_force_dpm_level()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Damdgpu_smu.h466 uint32_t *mclk_mask,