Searched refs:mmCP_CE_IC_OP_CNTL (Results 1 – 2 of 2) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx_v10_0.c | 2247 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2249 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2253 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
2524 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_ce_microcode()
2526 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); in gfx_v10_0_cp_gfx_load_ce_microcode()
2530 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_ce_microcode()
|
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 10256 #define mmCP_CE_IC_OP_CNTL … macro
|