Searched refs:mmCP_CPC_IC_BASE_CNTL (Results 1 – 9 of 9) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| H A D | amdgpu_smu8_smumgr.c | 205 mmCP_CPC_IC_BASE_CNTL); in smu8_load_mec_firmware()
211 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); in smu8_load_mec_firmware()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_8_0_d.h | 350 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
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| H A D | gfx_8_1_d.h | 350 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx_v10_0.c | 2936 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); in gfx_v10_0_cp_compute_load_microcode()
2940 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v10_0_cp_compute_load_microcode()
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| H A D | amdgpu_gfx_v9_0.c | 3283 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_0_cp_compute_load_microcode()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2604 #define mmCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 2808 #define mmCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_9_1_offset.h | 2874 #define mmCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_10_1_0_offset.h | 10262 #define mmCP_CPC_IC_BASE_CNTL … macro
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