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Searched refs:mmCP_GFX_MQD_CONTROL (Results 1 – 5 of 5) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v10_0.c2995 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); in gfx_v10_0_gfx_mqd_init()
3080 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); in gfx_v10_0_gfx_queue_init_register()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2654 #define mmCP_GFX_MQD_CONTROL … macro
H A Dgc_9_2_1_offset.h2840 #define mmCP_GFX_MQD_CONTROL … macro
H A Dgc_9_1_offset.h2906 #define mmCP_GFX_MQD_CONTROL … macro
H A Dgc_10_1_0_offset.h5050 #define mmCP_GFX_MQD_CONTROL … macro