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Searched refs:mmCP_MES_IC_BASE_CNTL (Results 1 – 2 of 2) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_mes_v10_1.c246 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); in mes_v10_1_load_microcode()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h10274 #define mmCP_MES_IC_BASE_CNTL … macro