Searched refs:mmCP_ME_IC_OP_CNTL (Results 1 – 2 of 2) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx_v10_0.c | 2210 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2212 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2216 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
2593 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_me_microcode()
2595 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); in gfx_v10_0_cp_gfx_load_me_microcode()
2599 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); in gfx_v10_0_cp_gfx_load_me_microcode()
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| /netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 10248 #define mmCP_ME_IC_OP_CNTL … macro
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