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Searched refs:mmCP_PQ_WPTR_POLL_CNTL1 (Results 1 – 11 of 11) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dpolaris10_pwrvirus.h1787 { 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1 },
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v9.c315 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), in kgd_gfx_v9_hqd_load()
H A Damdgpu_amdkfd_gfx_v10.c327 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), in kgd_hqd_load()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h265 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
H A Dgfx_7_2_d.h267 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
H A Dgfx_8_0_d.h298 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
H A Dgfx_8_1_d.h298 #define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2496 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
H A Dgc_9_2_1_offset.h2706 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
H A Dgc_9_1_offset.h2770 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro
H A Dgc_10_1_0_offset.h4836 #define mmCP_PQ_WPTR_POLL_CNTL1 … macro