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Searched refs:mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h1707 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … macro
H A Dgc_9_1_offset.h1765 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … macro
H A Dgc_10_1_0_offset.h3789 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … macro