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Searched refs:mmJPEG_CGC_CTRL (Results 1 – 7 of 7) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_jpeg_v2_5.c262 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
270 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
280 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
285 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
H A Damdgpu_jpeg_v2_0.c287 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_disable_clock_gating()
295 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v2_0_disable_clock_gating()
310 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_enable_clock_gating()
318 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v2_0_enable_clock_gating()
H A Damdgpu_vcn_v1_0.c449 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
458 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
576 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
583 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
647 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h156 #define mmJPEG_CGC_CTRL … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h336 #define mmJPEG_CGC_CTRL … macro
H A Dvcn_2_5_offset.h367 #define mmJPEG_CGC_CTRL … macro
H A Dvcn_2_0_0_offset.h352 #define mmJPEG_CGC_CTRL … macro