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Searched refs:mmSCRATCH_REG0_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h214 #define mmSCRATCH_REG0_BASE_IDX … macro
H A Dgc_9_0_offset.h4639 #define mmSCRATCH_REG0_BASE_IDX … macro
H A Dgc_9_2_1_offset.h4825 #define mmSCRATCH_REG0_BASE_IDX … macro
H A Dgc_9_1_offset.h4869 #define mmSCRATCH_REG0_BASE_IDX … macro
H A Dgc_10_1_0_offset.h7105 #define mmSCRATCH_REG0_BASE_IDX … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsoc15_common.h81 uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \