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Searched refs:mmSDMA0_RLC7_RB_WPTR (Results 1 – 3 of 3) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_offset.h974 #define mmSDMA0_RLC7_RB_WPTR … macro
H A Dsdma0_4_2_2_offset.h978 #define mmSDMA0_RLC7_RB_WPTR … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h960 #define mmSDMA0_RLC7_RB_WPTR … macro