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Searched refs:mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL (Results 1 – 14 of 14) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h80 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
H A Dsdma0_4_0_offset.h82 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 macro
H A Dsdma0_4_2_offset.h82 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
H A Dsdma0_4_2_2_offset.h82 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h167 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
H A Doss_3_0_1_d.h164 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
H A Doss_2_0_d.h230 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
H A Doss_3_0_d.h301 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_sdma_v2_4.c441 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
H A Damdgpu_cik_sdma.c464 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
H A Damdgpu_sdma_v3_0.c679 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
H A Damdgpu_sdma_v5_0.c633 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v5_0_gfx_resume()
H A Damdgpu_sdma_v4_0.c1418 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); in sdma_v4_0_start()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h54 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL … macro