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Searched refs:mmSDMA0_UTCL1_CNTL (Results 1 – 6 of 6) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h134 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_0_offset.h136 #define mmSDMA0_UTCL1_CNTL 0x003c macro
H A Dsdma0_4_2_offset.h136 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_2_2_offset.h136 #define mmSDMA0_UTCL1_CNTL … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_sdma_v5_0.c718 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_0_gfx_resume()
721 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_0_gfx_resume()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h108 #define mmSDMA0_UTCL1_CNTL … macro