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Searched refs:mmSDMA0_UTCL1_WR_XNACK0 (Results 1 – 5 of 5) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h152 #define mmSDMA0_UTCL1_WR_XNACK0 … macro
H A Dsdma0_4_0_offset.h154 #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 macro
H A Dsdma0_4_2_offset.h154 #define mmSDMA0_UTCL1_WR_XNACK0 … macro
H A Dsdma0_4_2_2_offset.h154 #define mmSDMA0_UTCL1_WR_XNACK0 … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h126 #define mmSDMA0_UTCL1_WR_XNACK0 … macro