Home
last modified time | relevance | path

Searched refs:mmSDMA1_GFX_RB_WPTR_POLL_CNTL (Results 1 – 10 of 10) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h303 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 macro
H A Doss_3_0_1_d.h392 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 macro
H A Doss_2_0_d.h344 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 macro
H A Doss_3_0_d.h496 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_offset.h216 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 macro
H A Dsdma1_4_2_2_offset.h216 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL … macro
H A Dsdma1_4_2_offset.h212 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_sdma_v4_0.c110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
H A Damdgpu_sdma_v5_0.c85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h1214 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL … macro