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Searched refs:mmUVD_JRBC_RB_WPTR (Results 1 – 8 of 8) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_jpeg_v2_5.c347 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_5_start()
350 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_start()
415 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_dec_ring_get_wptr()
433 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_5_dec_ring_set_wptr()
H A Damdgpu_jpeg_v1_0.c157 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v1_0_decode_ring_get_wptr()
171 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v1_0_decode_ring_set_wptr()
530 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v1_0_start()
535 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v1_0_start()
H A Damdgpu_jpeg_v2_0.c370 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_0_start()
373 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
436 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_dec_ring_get_wptr()
454 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
H A Damdgpu_vcn_v1_0.c1179 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in vcn_v1_0_stop_dpg_mode()
1314 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); in vcn_v1_0_pause_dpg_mode()
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h128 #define mmUVD_JRBC_RB_WPTR … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h264 #define mmUVD_JRBC_RB_WPTR … macro
H A Dvcn_2_5_offset.h139 #define mmUVD_JRBC_RB_WPTR … macro
H A Dvcn_2_0_0_offset.h124 #define mmUVD_JRBC_RB_WPTR … macro