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Searched refs:mmUVD_RB_WPTR3 (Results 1 – 5 of 5) sorted by relevance

/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h58 #define mmUVD_RB_WPTR3 0x3d1c macro
H A Duvd_7_0_offset.h132 #define mmUVD_RB_WPTR3 … macro
/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h292 #define mmUVD_RB_WPTR3 … macro
H A Dvcn_2_5_offset.h581 #define mmUVD_RB_WPTR3 … macro
H A Dvcn_2_0_0_offset.h482 #define mmUVD_RB_WPTR3 … macro